Tech Lead, Digital Design Engineer

Location: San Jose, California, United States

Department: Design Engineering CCE2

 

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. 

Job Description 

We are looking for Senior Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc. 

Basic Qualifications: 

• Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred. 

• +3 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage. 

• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. 

• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! 

• Authorized to work in the US and start immediately. 

Required Experience: 

• Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc. 

• Proven front end design skill – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc. 

• Block level ownership from architecture to GDS. 

• Experience with Synopsys and/or Cadence digital design tools/flows 

• Knowledge of design for test (DFT) 

• Familiarity with UVM based design verification 

• Silicon bring-up and debug experience 

• Small-geometry CMOS (≤28nm) design 

Preferred Experience: 

• Scripting with Python or other equivalent programming languages. 

• Development/support for PCIe or Ethernet Switch products.