Design Verification Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD. 

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. 

 

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

 

 

 

 

THE PERSON:

We are seeking a high‑impact Design Verification Engineer with strong technical depth, ownership, and the ability to drive verification closure on complex, high‑performance ASIC designs.
The ideal candidate brings hands‑on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading verification efforts across IP, subsystem, and SoC levels.

You will work in a fast‑paced, highly collaborative environment and contribute directly to the success of next‑generation AMD networking products.

 

KEY RESPONSIBILITIES:

 

Verification Architecture & Testbench Development

• Develop robust UVM‑based testbench architectures for IP, subsystem, and SoC‑level verification.
• Drive test plan creation, feature mapping, and coverage strategy for complex networking and data‑path IP.
• Develop high‑quality SystemVerilog components: stimulus generators, agents, BFMs/transactors, scoreboards, checkers, assertions, and functional coverage models.

 

 

Execution, Debug & Closure

• Own execution of verification plans, regression triage, and debug of architectural, functional, and performance issues.
• Root‑cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet), and system interactions.
• Optimize simulations, coverage closure, and verification sign‑off methodology.

Tools & Methodology

• Use industry‑standard simulation, debug, and analysis tools (VCS, Verdi/DVE, coverage tools, waveform analysis suites).
• Contribute to verification methodology improvements, automation, and infrastructure enhancements (Python/Tcl/Make).

Cross‑Functional Collaboration

• Collaborate closely with RTL design, architecture, validation, firmware, and emulation/HAPS teams to ensure high‑quality deliverables.
• Participate in design reviews, micro‑architecture definition, and bring a verification perspective into early design stages.
• Mentor junior engineers and provide technical leadership within the verification team.

 

LANGUAGES & TOOLS

Required

• Expert‑level knowledge of SystemVerilog and UVM
• Strong hands‑on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE)
• Proven experience in verifying complex IP/subsystems with test plans, coverage, and constrained‑random methodologies
• Strong debug skills across architecture, RTL, and testbench layers
• Experience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar data‑path components
• Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure

Preferred

• Packet-processing pipelines, switch fabrics, schedulers, packet buffers, or traffic managers.
• Experience with performance verification, power‑aware verification (UPF), or formal verification
• Familiarity with FPGA/HAPS‑based validation and acceleration flows
• Exposure to architectural modeling or C/C++ reference models

 

 

PREFERRED QUALIFICATIONS:

• Strong analytical and problem‑solving abilities with a proven track record of debugging complex issues
• Ability to lead verification tasks independently and drive cross‑team closure
• Excellent verbal and written communication skills
• Comfortable working in a fast‑paced, collaborative, multi‑site environment
• Ability to mentor and guide junior DV engineers

 

ACADEMIC CREDENTIALS

Bachelor’s Degree in Electrical/Computer Engineering or related field, Master’s Preferred

 

#LI-RD1

 

This role is not eligible for visa sponsorship.

 

Benefits offered are described: AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

THE ROLE:

 

 

 

 

THE PERSON:

We are seeking a high‑impact Design Verification Engineer with strong technical depth, ownership, and the ability to drive verification closure on complex, high‑performance ASIC designs.
The ideal candidate brings hands‑on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading verification efforts across IP, subsystem, and SoC levels.

You will work in a fast‑paced, highly collaborative environment and contribute directly to the success of next‑generation AMD networking products.

 

KEY RESPONSIBILITIES:

 

Verification Architecture & Testbench Development

• Develop robust UVM‑based testbench architectures for IP, subsystem, and SoC‑level verification.
• Drive test plan creation, feature mapping, and coverage strategy for complex networking and data‑path IP.
• Develop high‑quality SystemVerilog components: stimulus generators, agents, BFMs/transactors, scoreboards, checkers, assertions, and functional coverage models.

 

 

Execution, Debug & Closure

• Own execution of verification plans, regression triage, and debug of architectural, functional, and performance issues.
• Root‑cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet), and system interactions.
• Optimize simulations, coverage closure, and verification sign‑off methodology.

Tools & Methodology

• Use industry‑standard simulation, debug, and analysis tools (VCS, Verdi/DVE, coverage tools, waveform analysis suites).
• Contribute to verification methodology improvements, automation, and infrastructure enhancements (Python/Tcl/Make).

Cross‑Functional Collaboration

• Collaborate closely with RTL design, architecture, validation, firmware, and emulation/HAPS teams to ensure high‑quality deliverables.
• Participate in design reviews, micro‑architecture definition, and bring a verification perspective into early design stages.
• Mentor junior engineers and provide technical leadership within the verification team.

 

LANGUAGES & TOOLS

Required

• Expert‑level knowledge of SystemVerilog and UVM
• Strong hands‑on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE)
• Proven experience in verifying complex IP/subsystems with test plans, coverage, and constrained‑random methodologies
• Strong debug skills across architecture, RTL, and testbench layers
• Experience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar data‑path components
• Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure

Preferred

• Packet-processing pipelines, switch fabrics, schedulers, packet buffers, or traffic managers.
• Experience with performance verification, power‑aware verification (UPF), or formal verification
• Familiarity with FPGA/HAPS‑based validation and acceleration flows
• Exposure to architectural modeling or C/C++ reference models

 

 

PREFERRED QUALIFICATIONS:

• Strong analytical and problem‑solving abilities with a proven track record of debugging complex issues
• Ability to lead verification tasks independently and drive cross‑team closure
• Excellent verbal and written communication skills
• Comfortable working in a fast‑paced, collaborative, multi‑site environment
• Ability to mentor and guide junior DV engineers

 

ACADEMIC CREDENTIALS

Bachelor’s Degree in Electrical/Computer Engineering or related field, Master’s Preferred

 

#LI-RD1

 

This role is not eligible for visa sponsorship.

 

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

Tags: No, USD $145,600.00/Yr., USD $208,000.00/Yr., US Careers (External)