Senior Validation Engineer (Memory Validation)

Job Responsibilities:

The mission of this role is to validate all aspects of the memory subsystems on the ASIC and its systems using advanced high-speed test equipment and scalable automation platforms. This would include electrical validation of memory interfaces like DDR and validation of vendor memories for inter-operability. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar. As a memory validation engineer your responsibilities would include:

• Creating memory validation test plans.
• Using platform level tools and techniques to ensure performance to memory specifications.
• Executing of DDR memory stress tests in system and debug of failures.
• Interfacing with Architecture, Design, and Validation teams to review and address debug results.
• Developing software tools to support silicon bring-up of the memory subsystem, implementing special memory tests.
• Silicon early bring-up, investigating system DRAM issues and discovering workarounds.

Basic qualifications:

• Bachelor’s in Electrical Engineering or Computer Science is required, and a Master’s is preferred.
• 5+ years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Deep understanding of DDR technologies such as DDR, LPDDR, JEDEC standards.
• Experienced with implementing DRAM/memory controller initialization code, memory subsystem/DDR PHYs training/calibration software.
• Experience and interested in writing code to test IO devices and/or functional IP units.
• Familiarity with: boot code, computer system initialization, device drivers, SoC bring up, IO devices, debuggers, analysis tools (logic analyzers, oscilloscopes)
• Developing/executing test plan for pre and post silicon verification, designing and crafting targeted tests for validating specific memory controller functionality/ECOs.
• A strong background in bench automation techniques, especially Python.

Required experience:

• Experience defining validation plans for functional, signal and power integrity work HW and ASIC teams to debug complex memory issues.
• Experience in system testing, characterization and compliance, margin analysis and optimization.
• Experience working with memory vendors to identify issues, working with SOC to improve memory calibration and tuning sequences.
• Experience developing automation scripts and test tools for execution efficiency, repeatability, and reporting.
• Familiarity with memory standards and compliance testing.
• Comfortable using high speed oscilloscopes, logical analyzers, memory interposers.

Preferred experience:

• Extensive experience with memory debug techniques and methodologies
• Direct experience working on enterprise grade memory subsystem validation, diagnostics and tuning.
• Experience with DRAM memory vendors on DDR4 or DDR5.
• Experience with firmware-based operations of high-speed memory sub-systems, configurations of DRAM based memories.
• Good knowledge of SoC package, board design and related signal integrity.
• Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence.
• Previous experience working with major DRAM memory vendors and validation of DRAM device is also a plus.