HVM Principal Product Engineer

Overview: 
Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking a HVM Principal Product Engineer in Taipei, Taiwan. Partnering with leading processor vendors, cloud service providers, seasoned investors and world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning. For more information about Astera Labs, see www.AsteraLabs.com

Job Description:

As an Astera Labs Principal HVM Product Engineer, you will support products already in HVM (high volume manufacturing) at our Asia OSAT partners. You will be working closely with operations and engineering team to ensure smooth manufacturing and high-quality customer shipments. In this role, you will complement the New Product Introduction Product Engineers as products are released into production and own the engineering manufacturing and quality during mass production. Responsibilities included yield and test time improvement, test program stability, lot disposition, 2^nd source OSAT qualification, root causing and developing creative ways of manufacturing screening for high-speed signals such as XCVR.

Basic Qualifications:

• Minimum of 8 years of experience in the field of post silicon development dealing with high-speed XCVR (product, test or validation). 
• Strong academic/technical background in electrical or computer engineering; Bachelor’s is required; MS preferred
• Experience in working with PCIe Gen3 and above
• Strong problem-solving skills that involve system-level analysis with test hardware, test programs, and DUT.
• Digital and analog circuit-level understanding for DUT.
• Excellent team player with great communication skills.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks.

Required Experience:

• Hands-on experience with using the Advantest 93k ATE platform with specific skills in updating ATE test programs for wafer sort and final test solutions.
• Hands-on knowledge of NRZ/PAM4 SerDes protocols like PCIe (Gen 3 and above), Ethernet (25G and above), etc., and/or memory interfaces such as (LP)DDR5/4/3.
• Detailed mindset monitoring device ATE test yields, ATE test time, device quality, and rolling out new ATE test programs using consistent BKMs.
• Strong data analysis skills using tools such as JMP or Spotfire to calculate limits and drawing conclusions. 
• Hands-on experience in product level qualification for release to production.
• Energetic work mindset meeting the demands of shipping quality parts to Astera Labs’ customers through the manufacturing stage of development.

Preferred experience:

• Working with silicon validation teams to ensure device performance meets production requirements.
• Firmware development in C/C++, scripting in Python, or other equivalent programming experience.