Astera Labs

Senior System Validation Engineer

Santa Clara, CA
Machine Learning R Python Matlab

Astera Labs is a global leader delivering semiconductor-based connectivity solutions purpose-built to unleash the full potential of intelligent data infrastructure at cloud-scale. Our class-defining first-to-market products based on PCIe, CXL, and Ethernet technologies deliver critical connectivity for high-value artificial intelligence and machine learning applications. Our focus on customer-driven product definition and commitment to design solutions in the cloud, for the cloud, results in breakthrough execution and scale for our customers. We are headquartered in the heart of California’s Silicon Valley, with R&D centers and offices in Taiwan, China, Vancouver and Toronto, Canada, and Haifa, Israel.

Job Description

  • Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar.
  • Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
  • Formulate a comprehensive validation plan,  automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion
  • Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Education and Experience Requirements

  • Strong academic and technical background in electrical or computer engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
  • ≥5 years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.

Desired qualifications

  • Strong knowledge in scripting for automation of validation efforts (e.g. Python, Matlab)
  • Experience with silicon bring-up, debugging complex electrical and system performance issues, production ramp.
  • Very knowledgeable about common high-speed SerDes protocols like Ethernet, PCIe etc., and the electrical, system level specifications defined in the standard documents (IEEE802.3, PCIe Base Specification etc.)
  • Very knowledgeable about SerDes architecture including Tx/Rx equalization, adaptation, CDR, block level requirements and SerDes link jitter budget.
  • Experience working with lab equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes and VNA
  • Experience with PAM4 SerDes validation
  • Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.
  • Knowledge of Signal Integrity simulation tools
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
  • Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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