Principal Digital RTL Engineer

Location: San Jose, California, United States

Department: AMS Design

Principal Digital RTL Engineer

Location: San Jose, CA (Onsite)

Role Overview

As a Principal Engineer on our Analog/Mixed-Signal (AMS) Design team, you will architect and deliver the high-performance analog building blocks at the heart of Astera Labs' purpose-built connectivity silicon. From high-speed SerDes and PLLs to data converters and precision references, your circuits will directly enable the bandwidth, signal integrity, and power efficiency that rack-scale AI infrastructure demands.

This is a hands-on technical leadership role at a hyper-growth company defining the connectivity backbone of the AI era. You'll own designs from specification through silicon bring-up, set the technical direction for complex AMS blocks, and mentor engineers across the team — turning ambitious architecture into production-proven products that ship at scale.

Key Responsibilities

• Circuit Design & Architecture
  • Architect, design, and optimize high-speed analog/mixed-signal circuits such as SerDes, PLLs/clocking, ADCs/DACs, LDOs, and bias/reference blocks
  • Define block-level specifications and trade-offs for performance, power, area, and yield in advanced process nodes
  • Drive design methodology, reuse, and best practices across the AMS team
• Verification & Validation
  • Develop and execute simulation plans across PVT, Monte Carlo, and reliability corners to ensure first-pass silicon success
  • Partner with layout designers to guide floorplanning, matching, parasitics, and physical implementation
  • Lead silicon bring-up, characterization, and debug, correlating measured results to models and specifications
• Technical Leadership & Collaboration
  • Provide technical direction and mentorship to design engineers, elevating the capabilities of the broader team
  • Collaborate cross-functionally with digital, system, product, and packaging teams to deliver integrated solutions
  • Contribute to IP roadmaps, design reviews, and continuous improvement of the AMS design flow

Basic Qualifications

• MS or PhD in Electrical Engineering or a related field
• 8+ years of experience in analog/mixed-signal integrated circuit design
• Proven track record designing high-speed AMS blocks (e.g., SerDes, PLLs, data converters, references/regulators) through production silicon
• Strong command of transistor-level design, device physics, and analog design fundamentals in advanced CMOS nodes
• Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre) and scripting for design automation
• Demonstrated ability to take designs from specification through tape-out and silicon validation

Preferred Qualifications

• Experience with high-speed I/O and SerDes for connectivity standards such as PCIe, Ethernet, or UALink
• Deep understanding of physical-layer signal integrity, channel modeling, and equalization
• Hands-on lab experience with high-speed measurement and characterization equipment
• Familiarity with mixed-signal verification methodologies and analog/digital co-design
• Excellent communication skills and a collaborative, mentorship-driven approach in a fast-paced environment
  
  

  Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.