Silicon Design Verification Staff Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

 

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

THE ROLE:

PCIe SubSystem team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles. PCIe IP is one of the most important IP in all AMD’s projects. So, this role provides a great opportunity to work on the most advanced PCIe technology with the global team Architects/Designers/DV on PCIe SS IP Verification.

 

THE PERSON:

People who have the passion to work on leading edge technology, who have good communication skills will be preferred in this role.

 

KEY RESPONSIBILITIES:

• Develop and update infrastructure and environment for IP level design verification.
• Closely working with Design and Architecture team to develop new verification component
• Responsible for PCIe SS IP new features verification plan and verification closure

PREFERRED EXPERIENCE:

• Solid background with ASIC design verification flow and multiple ASIC tape out experience with 8+ years
• Team leading experience and experienced on testbench architecture.
• Solid knowledge on UVM, SystemVerilog , Verilog is a must
• Solid background on PCIe is preferred, other high speed IO protocol or Serdes PHY is also a big plus
• Low power verification work experience is a plus.
• Knowledge on formal verification is a plus.
• Fluent written English for technical discussion among global team, vocal is a plus

ACADEMIC CREDENTIALS:

• Candidate is preferred to be MSEE with 8+ years, or BSEE with 10+ years’ experience in digital ASIC/SOC design verification.

LOCATION:

Penang, Malaysia

 

#LI-KL1

#LI-Hybrid

Benefits offered are described: AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

THE ROLE:

PCIe SubSystem team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles. PCIe IP is one of the most important IP in all AMD’s projects. So, this role provides a great opportunity to work on the most advanced PCIe technology with the global team Architects/Designers/DV on PCIe SS IP Verification.

 

THE PERSON:

People who have the passion to work on leading edge technology, who have good communication skills will be preferred in this role.

 

KEY RESPONSIBILITIES:

• Develop and update infrastructure and environment for IP level design verification.
• Closely working with Design and Architecture team to develop new verification component
• Responsible for PCIe SS IP new features verification plan and verification closure

PREFERRED EXPERIENCE:

• Solid background with ASIC design verification flow and multiple ASIC tape out experience with 8+ years
• Team leading experience and experienced on testbench architecture.
• Solid knowledge on UVM, SystemVerilog , Verilog is a must
• Solid background on PCIe is preferred, other high speed IO protocol or Serdes PHY is also a big plus
• Low power verification work experience is a plus.
• Knowledge on formal verification is a plus.
• Fluent written English for technical discussion among global team, vocal is a plus

ACADEMIC CREDENTIALS:

• Candidate is preferred to be MSEE with 8+ years, or BSEE with 10+ years’ experience in digital ASIC/SOC design verification.

LOCATION:

Penang, Malaysia

 

#LI-KL1

#LI-Hybrid

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

Tags: No, MYR RM235,200.00/Yr., MYR RM336,000.00/Yr., Global Careers (do not use for US or Canada)