Staff Engineer, SoC DFX

AMD

Hybrid

Ottawa, ON

Full-time

Staff

$112k–$160kPosted 2mo ago

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Real job — pulled straight from AMD’s careers page · Verified August 8, 2026 · No reposts.

AMD is hiring a Staff Engineer, SoC DFX — a full-time, based in Ottawa, ON role ($112k–$160k). Apply directly on AMD's careers page below.

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE:

As part of the SoC (System-on-Chip) Design-for-Test (DFT) team, you will be responsible for implementing, verifying, optimizing, and deploying advanced DFT solutions across next-generation products. You will work closely with architecture, design, verification, physical design, and product engineering teams to ensure high-quality scan insertion and ATPG execution for complex SoCs.

This role offers the opportunity to drive test architecture, improve manufacturability and test quality, support silicon bring-up activities, and contribute to scalable DFT methodologies across a range of products.

THE PERSON: 

You are a motivated engineer with a strong understanding of DFT fundamentals and ASIC design flows. You enjoy solving complex technical challenges, applying strong analytical and debugging skills, and working collaboratively across multiple engineering disciplines. You communicate effectively, take ownership of problems, and maintain a strong focus on quality, coverage, and manufacturability.

KEY RESPONSIBILITIES: 

Drive end-to-end SoC-level scan insertion, DFT implementation, and ATPG execution.
Develop and optimize scan architectures, scan chains, test compression, and ATPG strategies.
Analyze scan coverage and ATPG results to improve test quality and coverage.
Support ATPG retargeting and hierarchical test integration methodologies.
Debug scan, ATPG, simulation, and emulation issues from block level through full-chip integration.
Develop and validate methodologies for stuck-at, transition, at-speed, and diagnostic pattern generation.
Collaborate with design, verification, physical design, CAD, and product engineering teams to resolve DFT-related challenges.
Support silicon bring-up, manufacturing test development, yield improvement, and failure analysis activities.
Contribute to DFT planning and implementation of technologies such as scan compression, memory built-in self-test (MBIST), logic built-in self-test (LBIST), PLL-based at-speed testing, and on-chip debug infrastructure.
Develop automation and scripting solutions to improve DFT productivity, quality, and scalability.

PREFERRED EXPERIENCE: 

Experience with scan insertion, ATPG, and DFT methodologies.
Strong knowledge of digital design fundamentals and ASIC development flows.
Experience with test compression technologies and hierarchical ATPG flows.
Experience debugging gate-level simulation, ATPG validation, and SoC integration issues.
Familiarity with Verilog/SystemVerilog and digital logic design.
Experience with scripting languages such as Python, Perl, Tcl, or Shell.
Experience with SoC-level ATPG retargeting methodologies.
Familiarity with emulation-based DFT validation and debug.
Experience with silicon bring-up, diagnosis, and yield analysis.
Knowledge of MBIST, LBIST, JTAG/IJTAG, Streaming Scan Network (SSN), or other advanced DFT methodologies.
Experience supporting large-scale GPU, CPU, AI accelerator, or complex ASIC development.

ACADEMIC CREDENTIALS: 

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

LOCATIONS:

Markham, Ottawa

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

THE ROLE:

THE PERSON: 

KEY RESPONSIBILITIES: 

Drive end-to-end SoC-level scan insertion, DFT implementation, and ATPG execution.
Develop and optimize scan architectures, scan chains, test compression, and ATPG strategies.
Analyze scan coverage and ATPG results to improve test quality and coverage.
Support ATPG retargeting and hierarchical test integration methodologies.
Debug scan, ATPG, simulation, and emulation issues from block level through full-chip integration.
Develop and validate methodologies for stuck-at, transition, at-speed, and diagnostic pattern generation.
Collaborate with design, verification, physical design, CAD, and product engineering teams to resolve DFT-related challenges.
Support silicon bring-up, manufacturing test development, yield improvement, and failure analysis activities.
Contribute to DFT planning and implementation of technologies such as scan compression, memory built-in self-test (MBIST), logic built-in self-test (LBIST), PLL-based at-speed testing, and on-chip debug infrastructure.
Develop automation and scripting solutions to improve DFT productivity, quality, and scalability.

PREFERRED EXPERIENCE: 

Experience with scan insertion, ATPG, and DFT methodologies.
Strong knowledge of digital design fundamentals and ASIC development flows.
Experience with test compression technologies and hierarchical ATPG flows.
Experience debugging gate-level simulation, ATPG validation, and SoC integration issues.
Familiarity with Verilog/SystemVerilog and digital logic design.
Experience with scripting languages such as Python, Perl, Tcl, or Shell.
Experience with SoC-level ATPG retargeting methodologies.
Familiarity with emulation-based DFT validation and debug.
Experience with silicon bring-up, diagnosis, and yield analysis.
Knowledge of MBIST, LBIST, JTAG/IJTAG, Streaming Scan Network (SSN), or other advanced DFT methodologies.
Experience supporting large-scale GPU, CPU, AI accelerator, or complex ASIC development.