ASIC Physical Design Engineer

- 8+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience
- Master's degree in Computer Science, Computer Engineering, or Electrical Engineering, or experience in low power design techniques
- Experience leading or solely developing methodology and scripts for physical synthesis
- Experience managing physical design deliverables with ASIC design partners or foundries
- Familiar UPF/SDC verification and DFT/ATPG test coverage
- Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs
- Experience with modern ASIC/FPGA design and verification tools
- Experience with SOC bring-up and post-silicon validation
- Experience with IR drop analysis and EM/reliability sign-off

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Join the team that delivers highly differentiated silicon into Ring and Blink battery-powered devices. Our RBKS ASIC team works on state-of-the-art SoCs in a vertically integrated environment to deliver products our customers love. an ASIC Physical Design Engineer on our RBKS ASIC team, you'll serve as the primary technical interface with our back-end design partners for Tethys and future ASIC programs. You will own the quality of physical design deliverables—from synthesis through timing closure and silicon bring-up—ensuring our custom chips meet PPA (power, performance, area) and ship on schedule.

Key job responsibilities
• Expertise in UPF implementation and verification
• Own and review physical design, layout, timing closure deliverables and package from back-end design partners • Drive physical implementation through synthesis, floorplanning, place and route, power/clock distribution, congestion analysis, and sign-off
• Provide DFT expertise including scan insertion, MBIST integration, and DFT coverage review
• Debug silicon failures during ATE testing and drive resolution with design partners
• Ensure PPA (power, performance, area) targets are met; perform IR drop analysis and physical verification
• Develop and improve physical design methodologies and automation scripts
• Evaluate third-party IP for physical implementation feasibility and provide recommendations
• Collaborate closely with RTL designers on architectural feasibility studies and physical-aware design trade-offs


A day in the life
You'll work across time zones with our ASIC design partners, reviewing implementation progress, analyzing timing reports, and driving closure on critical paths. When silicon returns, you'll be at the center of ATE debug, correlating failures to physical design root causes and coordinating fixes with partners.

About the team
We're a small, nimble ASIC team building Ring's custom silicon from the ground up. We work in a vertically integrated environment where you see your work directly impact the products millions of customers rely on daily.