Senior Electrical Engineer (FPGA / High-Speed / Mixed-Signal)

Location: San Jose CA, CA

Key Responsibilities
1. FPGA-Based System Architecture
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Define FPGA-centric system architectures for high-throughput data processing platforms
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Partition functionality across FPGA, ADC/DAC, and host interfaces
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Collaborate with FPGA/FW teams on interface definition, timing, and performance
2. High-Speed Digital & SerDes Design
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Design and integrate high-speed interfaces including:
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DDR4/DDR memory subsystems
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PCIe Gen3/Gen4 interfaces
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QSFP (10G/25G/40G/100G) links
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10G+ SerDes channels
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Define routing constraints, stack-up, and impedance control
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Ensure signal integrity, timing closure, and link stability
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3. Mixed-Signal & Analog Front-End Design
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Design and integrate:
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High-speed ADC/DAC signal chains
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Data Converter Architectures (DCA)
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Precision analog front-end (AFE) circuits
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Develop circuits using low-noise OpAmps, filters, and gain stages
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Optimize performance metrics such as SNR, ENOB, bandwidth, and jitter sensitivity
4. Power System Design
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Design multi-rail DC/DC power systems for FPGA and high-speed circuits
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Manage power sequencing, noise, ripple, and efficiency
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Ensure power integrity for sensitive ADC and high-speed SerDes subsystems
5. Hardware Design & PCB Implementation
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Own schematic design and hardware architecture (Xpedition preferred)
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Guide PCB layout for high-layer-count, high-speed boards
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Lead design reviews focusing on SI/PI/EMI risks
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Ensure manufacturability (DFM) and testability (DFT)
6. System Bring-up & Debug
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Lead board bring-up and system integration:
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DDR training
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PCIe and SerDes link-up
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ADC performance validation
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Debug issues related to:
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Signal integrity
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Jitter and noise
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Power coupling and system interaction
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Use lab tools such as oscilloscopes, TDR/VNA, and protocol analyzers
7. Cross-Functional Collaboration
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Work closely with FPGA, firmware, software, mechanical, and system engineering teams
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Align electrical design with system-level performance requirements
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Drive cross-domain trade-offs
8. Technical Leadership
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Lead architectural decisions and technical reviews
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Mentor junior engineers in high-speed and mixed-signal design
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Drive structured problem-solving across complex systems
Required Qualifications
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Bachelor’s or Master’s degree in Electrical Engineering or related field
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8–12+ years of experience in high-speed, FPGA, or mixed-signal systems
Core Technical Requirements
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FPGA-based system design experience
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DDR4 memory subsystem design experience
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PCIe / SerDes / high-speed link experience
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ADC and analog front-end design experience
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DC/DC power system design experience
Fundamentals
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Strong understanding of:
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Signal Integrity (SI)
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Power Integrity (PI)
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High-speed timing and jitter analysis
Preferred Qualifications
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Hands-on experience with FPGA platforms (Intel / Xilinx)
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Experience with:
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High-speed data converters
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Optical interfaces / QSFP modules
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JESD204 or similar high-speed data links
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Strong PCB design experience with high-speed constraints
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Experience with tools such as:
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Xpedition (Mentor / Siemens)
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SI/PI analysis tools
Strong Plus
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Experience in semiconductor equipment, imaging, or instrumentation systems
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Experience with multi-board or modular systems
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Understanding of signal-power-thermal coupling effects
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Full product lifecycle experience (R&D → NPI → production)
Soft Skills
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Strong ownership mindset and accountability
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Ability to solve complex multi-domain engineering problems
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Excellent communication and cross-functional collaboration skills