Senior Manager, ASIC Development Engineering - STA Function

Company Description

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Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data.

Job Description

Position Overview:

We are seeking a highly skilled and experienced Senior Manager for our Static Timing Analysis (STA) function. The successful candidate will lead a team of talented engineers responsible for ensuring the timing performance and integrity of our complex semiconductor designs. This role requires a deep understanding of STA methodologies, exceptional leadership skills, and a strategic vision to drive continuous improvement in our timing analysis processes.

Key Responsibilities:

- Lead and manage the STA team, providing direction, mentorship, and support to ensure high performance and professional growth.

- Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs.

- Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance.

- Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes.

- Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance.

- Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the team’s workflow.

- Manage project timelines, resources, and deliverables to meet project milestones and deadlines.

- Prepare and present detailed timing reports and technical documentation to stakeholders and senior management.

- Foster a culture of innovation, collaboration, and continuous improvement within the STA team.

Qualifications

Qualifications:

- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

- A minimum of 15 years of experience in Static Timing Analysis, with at least 3 years in a leadership role.

- Proven track record of successfully leading STA teams and delivering complex IC designs to market.

- In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus, ANSYS PathFinder) and methodologies.

- Strong understanding of digital design principles, physical design, and semiconductor fabrication processes.

- Excellent problem-solving skills and the ability to think strategically and analytically.

- Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.

- Strong project management skills, with the ability to prioritize tasks and manage multiple projects simultaneously.

- A proactive, results-oriented mindset with a passion for innovation and continuous improvement.

- Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable.

Additional Information

Western Digital thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.

Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at staffingsupport@wdc.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.