Western Digital

Senior Engineer, ASIC Development Engineering (DFT)

Bengaluru, India
C++ Perl Python
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Description

Company Description

At Western Digital, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible.

At our core, Western Digital is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we’ve been doing just that. Our technology helped people put a man on the moon.

We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world’s biggest companies and public cloud, Western Digital is fueling a brighter, smarter future.

Binge-watch any shows, use social media or shop online lately? You’ll find Western Digital supporting the storage infrastructure behind many of these platforms. And, that flash memory card that captures and preserves your most precious moments? That’s us, too.

We offer an expansive portfolio of technologies, storage devices and platforms for business and consumers alike. Our data-centric solutions are comprised of the Western Digital®, G-Technology™, SanDisk® and WD® brands.

Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data.

Job Description

As part of the ASIC modeling team, the candidate will work on developing, maintaining and testing the NAND/SoC models using C/C++/SystemC. The SoC models capture the register accurate functionality of the controller chip which manages the NAND storage. 

    Qualifications

    Experience: 

    2+ years 

     

    Must have: 

    Experience in DFT implementation, Verification

    Experience in MBIST implementation, Verification

    Strong DFT/MBIST fundamentals 

    DRC Clean up |  Coverage improvement | Understanding and modifying MBIST algorithms 

    Pattern validation flows | Zero/Unit delay | SDF based 

     

    Good to have: 

    PERL/TCL Scripting /Python

    Usage of assertions for monitoring clock frequencies and other test related registers 

    Yield analysis and improvement flow 

    Understand CLP constructs and can work in multi-voltage, multi-power design 

     

    Expected Roles: 

    Need to architect DFT based on the PETE, Design and Customer specifications 

    Should be self motivated, self driven  and eager to learn 

    Qualifications

    BE/Btech//Mtech/ME

    Additional Information

    Western Digital thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.

    Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at staffingsupport@wdc.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

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