Principal Engineer, ASIC Development Engineering (DFT CAD Lead)

Company Description

The future. It’s on you. You & Western Digital.

We’ve been storing the world’s data for more than 50 years. Once, it was the most important thing we could do for data. Now we’re helping the world capture, preserve, access and transform data in a way only we can.

The most game-changing companies, consumers, professionals, and governments come to us for the technologies and solutions they need to capture, preserve, access, and transform their data.

But we can’t do it alone. Today’s exceptional data challenges require your exceptional skills. It’s You & Us. Together, we’re the next big thing in data. 
 
Western Digital® data-centric solutions are found under the G-Technology™, HGST, SanDisk®, Tegile™, Upthere™, and WD® brands.

Job Description

We are seeking a highly skilled and experienced engineer to develop and enhance Design for Testability (DFT) flows and methodologies. The ideal candidate will play a key role in advancing the CAD toolchain within the Design Enablement Group, ensuring efficient and effective DFT practices for complex SoC designs. This role requires in-depth knowledge of DFT concepts, test architecture, and flow automation, and hands-on experience in building and maintaining robust DFT flows.

Key Responsibilities:

• Develop, enhance, and maintain DFT flows and methodologies to optimize testability and fault coverage in semiconductor devices.
• Collaborate with cross-functional teams (Design, Verification, Test Engineering, CAD) to define and implement efficient DFT strategies and workflows.
• Integrate various test strategies such as scan insertion, Built-In Self-Test (BIST), Memory BIST (MBIST), Boundary Scan, and JTAG into the design flow.
• Automate and customize DFT CAD flows using scripting languages (Tcl, Python, Perl) to improve productivity and reduce design cycle times.
• Drive continuous improvements in the DFT flow to support evolving design complexities, process nodes, and packaging technologies.
• Ensure the scalability of DFT methodologies for multi-million gate SoCs, advanced packaging solutions, and chiplets (system of chips).
• Provide technical leadership and mentorship to junior engineers and collaborate with EDA tool vendors for tool improvements.
• Develop and maintain DFT documentation, design guidelines, and best practices for various design teams.
• Analyze test coverage data, debug test failures, and ensure compliance with industry standards and design specifications.
• Collaborate in tape-out readiness reviews and support silicon bring-up and failure analysis post-silicon.

Qualifications

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• Experience: 8-10 years of experience in Design for Testability (DFT) flow/methodology development in a semiconductor or EDA environment.
• Strong expertise in DFT concepts such as scan insertion, ATPG, BIST, MBIST, JTAG, and fault grading.

Additional Information

Because Western Digital thrives on the power of diversity and is committed to an inclusive environment where every individual can thrive through a sense of belonging, respect, and contribution, we are committed to giving every qualified applicant and employee an equal opportunity.  Western Digital does not discriminate against any applicant or employee based on their protected class status and complies with all federal and state laws against discrimination, harassment, and retaliation, as well as the laws and regulations set forth in the "Equal Employment Opportunity is the Law" poster.