We are looking for an experienced Senior Design Verification Engineer with strong expertise in SystemVerilog (SV) and UVM-based verification to drive verification activities for complex IP and SoC designs.

The ideal candidate will have hands-on experience executing multiple IP and SoC verification projects, developing robust verification environments, creating verification plans, debugging functional and gate-level simulations, and driving coverage closure. Experience with at least one industry-standard protocol such as Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, or DDR is required.

Key Responsibilities

• Develop and execute comprehensive design verification strategies and plans for IP and SoC projects.
• Translate functional and technical requirements into detailed verification plans, test scenarios, and coverage objectives.
• Develop scalable and reusable SystemVerilog/UVM verification environments.
• Build UVM components including testbenches, agents, drivers, monitors, sequencers, scoreboards, and coverage models.
• Set up, configure, execute, and debug functional and gate-level simulations.
• Develop and maintain automated regression environments for large verification programs.
• Analyze simulation failures, identify root causes, and collaborate with RTL and design teams to resolve issues.
• Verify designs using industry-standard protocols such as Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, DDR, or equivalent protocols.
• Evaluate, integrate, configure, and validate third-party Verification IP (VIP).
• Develop effective test strategies for functional, corner-case, error, and protocol-specific scenarios.
• Perform functional and code coverage analysis and drive coverage closure.
• Identify verification gaps and develop additional tests, assertions, or coverage models where required.
• Review simulation results, regression trends, coverage reports, and verification metrics.
• Improve verification infrastructure, methodologies, automation, and regression efficiency.
• Collaborate with RTL, architecture, firmware, emulation, and other engineering teams throughout the verification lifecycle.
• Participate in design and verification reviews and contribute technical recommendations.
• Maintain verification documentation, test plans, environments, results, and closure reports.
• Mentor junior verification engineers and contribute to verification best practices and methodology improvements.

What Makes You a Great Fit

• 7+ years of professional experience in ASIC, SoC, IP, or semiconductor design verification.
• Proven experience executing at least 3 IP or SoC verification projects from planning through verification closure.
• Strong hands-on expertise in SystemVerilog and UVM methodology.
• Experience developing and maintaining reusable UVM-based verification environments.
• Strong experience translating functional requirements into verification plans and test strategies.
• Hands-on experience setting up and debugging functional and/or gate-level simulations.
• Strong experience developing verification environments and automated regression setups.
• Practical experience with functional coverage, code coverage, coverage analysis, and coverage closure.
• Experience evaluating and integrating third-party VIPs into verification environments.
• Strong understanding of digital design, RTL concepts, simulation, debugging, and verification methodologies.
• Hands-on experience with at least one industry-standard protocol such as Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, or DDR.
• Strong debugging, analytical, and problem-solving capabilities.
• Ability to investigate complex simulation failures and identify root causes across RTL, testbench, and verification environments.
• Experience with industry-standard simulators and verification tools is desirable.
• Strong scripting or automation skills using languages such as Python, Perl, or Tcl are an advantage.
• Excellent communication and collaboration skills with the ability to work effectively across design and verification teams.
• Strong ownership mindset with the ability to independently drive verification activities from planning through coverage closure.