Analog Layout

Location: Delhi, Delhi, India

Department: Weekday's Client via platform

Workplace: on_site

Employment Type: full

Description

𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟭𝟬𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟱𝟬𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟭𝟬-𝟱𝟬 𝗟𝗣𝗔)

Experience: 4+ yrs

Location: India

Job Type: Full-time

We are seeking an experienced Analog Layout Engineer to design and implement high-performance analog and mixed-signal layouts for advanced semiconductor technologies. This role is ideal for professionals with strong expertise in full-custom analog layout, physical verification, and layout optimization who are passionate about developing silicon-proven designs for next-generation integrated circuits.

As an Analog Layout Engineer, you will collaborate closely with Analog Design, CAD, Physical Verification, and Process Engineering teams to develop robust, manufacturable layouts that meet stringent performance, reliability, and quality requirements. You will take ownership of layouts from block-level implementation through tape-out while ensuring compliance with advanced process technologies and industry-standard design methodologies.

Requirements

Key Responsibilities

• Design and implement high-quality full-custom analog and mixed-signal layouts for advanced technology nodes.
• Develop optimized layouts using device matching, common-centroid placement, symmetry, interdigitation, shielding, guard rings, and dummy device techniques.
• Perform floorplanning and optimize layouts for area, performance, manufacturability, and long-term reliability.
• Execute physical verification activities including DRC, LVS, ERC, and PEX closure using industry-standard verification tools.
• Collaborate with Analog Design, CAD, Physical Verification, and Process teams to resolve layout challenges and improve design quality.
• Ensure layouts comply with process design rules, reliability guidelines, and foundry requirements.
• Support tape-out activities, layout reviews, and implementation of engineering change requests.
• Debug layout-related issues and recommend improvements that enhance performance and manufacturability.
• Document layout methodologies, maintain design quality standards, and deliver projects within established timelines.
• Contribute to continuous improvement initiatives focused on layout methodologies, automation, and design efficiency.

What Makes You a Great Fit

• 4+ years of hands-on experience in Analog Layout and full-custom analog or mixed-signal IC design.
• Strong expertise with Cadence Virtuoso Layout XL/GXL and full-custom layout development.
• Excellent understanding of device matching, common-centroid layout, interdigitation, symmetry, shielding, guard rings, and dummy device implementation.
• Hands-on experience performing DRC, LVS, ERC, and PEX closure using Calibre or Cadence Pegasus.
• Experience working with advanced semiconductor technologies including FinFET and process nodes such as 16nm, 12nm, 7nm, 5nm, 3nm, or 2nm.
• Strong knowledge of electromigration (EM), IR drop, ESD protection, latch-up prevention, and semiconductor reliability guidelines.
• Proven experience owning layouts from block-level implementation through successful tape-out.
• Exposure to high-performance analog IPs such as PLL, ADC, DAC, Bandgap, LDO, PMIC, SerDes, Memory, or high-speed interfaces is an added advantage.
• Familiarity with scripting languages such as SKILL, Python, Perl, or TCL, along with knowledge of EM/IR analysis and advanced layout methodologies, is desirable.
• Strong analytical, debugging, communication, and cross-functional collaboration skills with a commitment to delivering high-quality, silicon-ready designs.