Real job — pulled straight from VoltAI’s careers page · Verified October 23, 2026 · No reposts.
Job description
VoltAI is hiring a Design for Test Engineer — a full-time, based in Palo Alto, CA role. Apply directly on VoltAI's careers page below.
Design for Test (DFT) Engineer
Department: Chips & Silicon
Location: Palo Alto Office
Employment Type: FullTime
About Voltai
Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.
About the Team
Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.
About this Role
You'll make sure the chips we work on can be tested in manufacturing and in the field. You'll own DFT architecture and implementation on real silicon programs with leading semiconductor companies while helping Voltai's AI learn DFT methodology.
What You’ll Do
Define DFT architecture for SoCs and IP, including scan, compression, MBIST, LBIST, and boundary scan.
Insert and verify DFT logic, and generate ATPG patterns that meet coverage targets.
Work with RTL, synthesis, and physical design teams to close DFT timing and area impact.
Support silicon bring-up, pattern debug, and yield analysis with test and product engineering.
Build automation for DFT flows and coverage reporting.
Help define how AI can accelerate DFT insertion and pattern generation.
What We’re Looking For
5+ years of DFT experience on production tapeouts.
Hands-on experience with Tessent, TestMAX, or Modus.
Strong knowledge of scan, compression, ATPG, MBIST, and IEEE 1149.1/1687.
Experience with DFT verification and gate-level simulation.
Tcl and Python scripting.
Bonus Points
Post-silicon test bring-up and ATE experience.
Experience with 2.5D/3D or chiplet test strategies.
Interest in AI-assisted design tools.
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Frequently asked questions
What skills are required for Design for Test Engineer at VoltAI?
The required skills for Design for Test Engineer at VoltAI include: Python.
What is the seniority level for Design for Test Engineer at VoltAI?
Design for Test Engineer at VoltAI is a Senior level position.
How do I apply for Design for Test Engineer at VoltAI?
You can view the full description and apply for Design for Test Engineer at VoltAI on EchoJobs: https://echojobs.io/job/voltai-design-for-test-dft-engineer-w78di.