Staff CPU RTL Engineer, Shared Cache

Tenstorrent is looking for an experienced Cache RTL design engineer to join this innovative team as a technical expert. In this role, the candidate will develop and implement the highest performance, most energy efficient cache and fabric designs in the industry. This person will be a key contributor for developing Tenstorrent’s next generation of cores and caches. This role requires creativity and innovation, along with excellent verbal and written communication skills. The ideal candidate has strong analytical thinking and problem-solving skills and enjoys using those skills to accomplish goals.

This role is Hybrid, based out of Austin, TX, or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• RTL coding in Verilog leveraging on both industry tools as well as open-source infrastructure 
• Play a key role in the microarchitecture, design and development of processor L2 and LLC (Last Level Cache) for high-performance computing systems.
• Design and micro architect Caches as driven by capacity, latency, bandwidth, and RAS requirements
• Drive trade-offs for your logic by working closely with performance, DV and physical design engineers to craft optimal solutions that meet the design goals 
• Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL and evaluate synthesis, timing and power results 
• Debug RTL/logic issues across various hierarchies (ex: core, chip) in both pre-silicon and post-silicon environment

Experience & Qualifications:

• BS/MS/PhD in EE/ECE/CE/CS with at least 8 years of experience 
• Experience in Cache, Multi-processor coherency microarchitecture, CHI protocol. Familiarity with AXI recommended but not required.
• Experience with computer architecture/system components/network/fabrics as a part of a CPU, ASIC or SOC design team 
• Expertise in logic design and ability to evaluate functional, performance, timing and power aspects of design.
• Strong experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator) 
• Experience in microarchitecture definition and specification development 
• Prior experience in industry standard ISAs – ARM, RISC-V, or X86.
• Strong problem solving and debug skills across various levels of design hierarchies

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.

Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.