Sr Staff Engineer, CPU System Microarchitect
Location: Bengaluru, Karnataka, India
Department: RISC V
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
We are looking for a talented engineer to join our CPU design team to define and implement CPU system RTL. You’ll work to combine multiple cores, multiple clusters of cores, fabrics and subsystem components together, collaborating with DV, PD, architecture and performance teams to deliver a functional, timing, and power-converged design.
This role is hybrid, based out of Bengaluru, India.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- An experienced micro-architect who thrives in building CPU systems (multiple cores, multiple clusters of cores and subsystem components) from scratch.
- Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
- Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
- Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.
What We Need
- 10+ years of industry experience with strong CPU systems RTL and microarchitecture background.
- Collaborate closely with DV, PD, architecture and performance engineers to meet functional, timing, and power goals.
- Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
- Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
- Enhance RTL design environment, tools, and methodologies to improve development efficiency.
What You Will Learn
- End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
- How to design and optimize a custom RISC-V CPU system from first principles.
- Integration of open-source and industry-standard tools to improve RTL flows and results.
- Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
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