Senior Chiplet Physical Design Engineer

We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better.

In this role, you will be responsible for synthesis and place and route using industry standard tools for high-speed CPU core design. Knowledge of cutting edge silicon technology 5nm and lower and multi Ghz design is a plus.

This role is based out of Tokyo, Japan.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Synthesis and Place and Route using industry standard tools for high speed CPU core design
• Plan out resources, schedule, project PPA
• Develop strategies to deliver reproducible design convergence results
• Help to create and refine synthesis and PNR flow for the project team
• Perform all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks and design closure
• Develop and recommend better design methodologies to enable better timing convergence
• Plan out resources, schedule, project PPA
• Guide and mentor junior engineers
• PV convergence (including static timing and power analysis)
• Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks
• Scripting in an interpreted language, minimum TCL in addition to at least one other

Experience & Qualifications:

• Bachelor, Master or PhD degree in electrical, computer engineering or computer science
• At least 10 years of relevant industry experience
• Experience with integrated circuit design tools (e.g. Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
• Experience with PV convergence, including static timing and power analysis
• Experience with chip physical design verification, including formal equivalence, timing, electrical rules, DRC/LVS, noise and electro-mitigation checks
• Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools
• Strong experience in SoC/ASIC/GPU/CPU design flows on taped out designs
• Expertise in timing closure and block/chip levels and ECO flows
• Experience with scripting in an interpreted language (Python, TCL)
• Willingness to work with others in a highly complex decision space
• Skills at developing an implementation plan, monitoring key indicators and communicating resource needs, as well as scoping risk to deliver value on schedule
• Excellent verbal and written communication in English, and collaboration skills

Nice to have

• Fluency in Japanese.
• Japanese work visa.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government.

As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.