Principal RTL Design Engineer, Network-on-chip (NoC)

We are seeking a highly skilled and experienced Principal RTL Design Engineer to join our team, focusing on Network-on-Chip (NoC) design. In this role, you will play a critical part in architecting and implementing high-performance, scalable NoC solutions that are integral to the efficiency of our AI processors. You will collaborate closely with cross-functional teams to ensure our NoC designs meet the stringent performance, power, and area requirements of our cutting-edge products.

This role is hybrid, based out of Belgrade, Serbia or Toronto, Ontario.

Responsibilities:

• Take ownership of key components within our Network-on-Chip (NoC), driving their design and development.
• Define and architect NoC specifications and micro-architectures in collaboration with system architects and other design engineers.
• Optimize NoC designs for performance, power, and area, ensuring efficient data movement and low latency.
• Develop and maintain RTL code in Verilog/SystemVerilog, ensuring high coding standards and best practices.
• Conduct thorough design verification and validation, including simulation, emulation, and formal verification.
• Collaborate with physical design teams to ensure successful integration and implementation of NoC components.
• Drive design reviews and provide technical guidance and mentorship to junior engineers.
• Work closely with software and hardware teams to define and implement system-level features and enhancements.
• Contribute to the development of design methodologies and flows to improve efficiency and quality.

Experience & Qualifications:

• Degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of experience in RTL design, with a strong focus on Network-on-Chip (NoC) architectures.
• Proven expertise in Verilog/SystemVerilog and RTL design principles.
• Deep understanding of NoC design, including routing algorithms, flow control, arbitration, and topology.
• Experience with performance analysis and optimization of NoC systems.
• Familiarity with design verification methodologies and tools (SystemVerilog Assertions, UVM, C-DPI, etc.).
• Experience with synthesis, timing analysis, and physical design considerations.
• Strong problem-solving skills and the ability to work independently and as part of a team.
• Excellent communication and interpersonal skills, with a track record of leading and mentoring engineering teams.
• Experience with high-performance computing or AI/ML accelerator architectures - preferred.
• Experience and/or understanding of low-level firmware written in C/C++ - preferred.
• Experience with system-level modeling and simulation tools - preferred.
• Familiarity with high-level synthesis (HLS) tools and methodologies - preferred.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government.

Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.