Formal Verification Engineer

Location: Santa Clara, California, United States; Spain

Department: Architecture: Design Verification

Tenstorrent is looking for a Formal Verification Engineer to help ensure the correctness of our next generation of high-performance RISC-V CPUs and AI compute platforms. You’ll use formal methods to prove complex hardware behavior, uncover corner cases that simulation may miss, and give architects and RTL designers confidence in the correctness of their designs. You’ll work closely with CPU architects, RTL designers, and other DV engineers to develop properties, build formal verification environments, analyze failures, and drive issues to closure. This is a hands-on opportunity to apply formal techniques to challenging problems in modern processor design.

This role is remote, based out of North America or Spain.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

 

Who You Are

• A verification engineer who enjoys solving complex problems and finding bugs that are difficult to expose through traditional simulation.
• Comfortable thinking about hardware behavior in terms of properties, invariants, assumptions, assertions, and proofs.
• A strong debugger who can analyze counterexamples, understand RTL behavior, and determine the root cause of failures.
• Collaborative and curious, with an interest in working closely with architects and RTL designers to improve design quality.
• Excited by the challenges of verifying high-performance CPUs and complex digital hardware.

What We Need

• 6+ years of experience in design verification, formal verification, or related RTL verification for CPUs, SoCs, ASICs, or complex digital designs.
• Hands-on experience with formal verification methodologies and tools, including property checking, assertions, assumptions, constraints, and coverage analysis.
• Strong SystemVerilog skills, including experience writing and debugging SVA.
• Solid understanding of digital design and computer architecture; experience with CPU pipelines, caches, interfaces, control logic, or other complex microarchitecture is highly valuable.
• Strong programming and scripting skills in Python, Tcl, C/C++, or similar, with excellent debugging and problem-solving abilities.

What You Will Learn

• Gain deep experience applying formal verification to high-performance, out-of-order RISC-V CPU designs.
• Learn how to identify which hardware behaviors are best verified through formal methods versus simulation, emulation, and other DV techniques.
• Develop expertise in writing scalable properties and proofs for complex control logic and interacting microarchitectural blocks.
• Learn how architectural intent translates into formal properties, assumptions, and measurable verification goals.
• Work alongside world-class CPU architects and RTL engineers on next-generation processors for AI, HPC, and high-performance computing.

 

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.