Director, Design for Test (DFT) Engineering

We are seeking a highly experienced and strategic Director of Design for Test (DFT) Engineering to lead our DFT team in developing high-performance solutions for industry-leading AI/ML architectures. This role is responsible for driving the overall DFT strategy and execution while leading a team of engineers working across multiple IPs and SoCs. The ideal candidate will provide technical and people leadership, ensuring best-in-class test coverage, yield learning, and silicon debug capabilities while minimizing design overhead.

This role is hybrid and based out of Austin, TX or Santa Clara, CA.

We welcome leaders at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Lead and grow a team of DFT engineers, providing mentorship, performance management, and career development.
• Define and drive the DFT strategy, roadmap, and execution across multiple projects, ensuring high-quality and cost-effective test solutions.
• Collaborate cross-functionally with architecture, RTL design, physical design, verification, and test engineering teams to optimize DFT implementations.
• Oversee the development and deployment of DFT methodologies to improve efficiency, coverage, and silicon debug capabilities.
• Drive continuous improvement in test cost reduction, yield learning, and fault coverage while balancing design complexity.
• Work closely with manufacturing, test engineering, and post-silicon teams to facilitate silicon bring-up, debug, and yield optimization.
• Stay ahead of industry trends and ensure the team is leveraging state-of-the-art DFT techniques and tools.
• Manage project timelines, resource allocation, and risk mitigation strategies for DFT execution.

Experience & Qualifications:

• BS/MS/PhD in EE, ECE, CE, or CS with 12+ years of industry experience, including 5+ years in a leadership or management role.
• Proven track record of leading DFT teams in high-performance ASIC designs targeting advanced FinFET process nodes.
• Deep expertise in DFT architectures and methodologies, including ATPG, JTAG, Scan Compression, MBIST, and ASST implementation.
• Strong understanding of DFT CAD tools from major EDA vendors (Synopsys, Mentor, Cadence).
• Experience with low-power design flows (power gating, voltage scaling) and their impact on DFT.
• Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.
• Experience with post-silicon testing, debug, and yield analysis.
• Strong cross-functional collaboration, leadership, and communication skills with the ability to drive alignment across teams.
• Experience managing project timelines, budgets, and resource planning for DFT execution.