Alternate Job Titles:

• Staff Memory Layout Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an expert in memory layout design, with hands-on experience in SRAM, ROM, and eDRAM at the transistor and cell level. Comfortable with advanced layout tools and foundry process rules, you excel at optimizing for area, yield, and performance. You enjoy solving challenging DRC/LVS and reliability issues, collaborating across teams, and mentoring others. Your communication skills and attention to detail make you a trusted team member, eager to help deliver industry-leading memory IP.

What You’ll Be Doing:

• Lead the physical layout design of advanced memory IP (SRAM, ROM,eDRAM, etc.) at cell, array, and peripheral levels
• Ensure compliance with foundry process design rules (DRC/LVS) and memory-specific constraints
• Optimizelayouts for area, performance, power, yield, and manufacturability
• Perform RC extraction, parasitic analysis, and signal integrity verification for dense memory arrays
• Debug and resolve LVS/DRC and memory-specific issues efficiently
• Work cross-functionally with circuit, verification, and process teams to deliver first-pass silicon success
• Addressing reliability concerns (EM, IR drop, soft errors) in layouts
• Mentoring junior engineers and sharing best practices

The Impact You Will Have:

• Delivering robust, high-performance memory IP for top tech companies
• Reducing risk and time-to-market with first-pass silicon success
• Driving innovation in layout methodologies and automation
• Elevating team capability and quality

• Supporting Synopsys’ leadership in memory IP
• Empowering customers’ innovation in AI and advanced systems

What You’ll Need:

• Bachelor’s orMaster’sdegreein Electronics Engineering, Telecommunication, Physics, or related fields.
• Minimum of 5 years of experience in layout design.
• Deep memory layout knowledge (SRAM, ROM,eDRAM, etc.)
• Proficiencywith Custom Compiler, IC Compiler, Virtuoso
• Understanding of process rules, DRC/LVS, and memory constraints
• Experience with RC extraction, parasitic reduction, and signal integrity
• Ability to debug andoptimizeformanufacturability and reliability

Who You Are:

• Detail-oriented and analytical
• Collaborative and communicative
• Innovative and proactive
• Supportive mentor and team player

The Team You’ll Be A Part Of:

Join our memory layout team, dedicated to delivering high-quality, high-performance memory IP for next-generation chips. We thrive on innovation, quality, and teamwork, shaping the future of semiconductor technology.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.