Sr Staff Applications Engineer, HAV Solutions

Location: Sunnyvale, California, United States

We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

• Lead technical deployments of HAPS-200 and ProtoCompiler for strategic customers building billion-gate SoCs across AI/ML, automotive, hyperscaler, and aerospace segments
• Drive the full ASIC-to-FPGA flow including partitioning, clock conversion, synthesis, place-and-route, timing closure, bitstream generation, and hardware bring-up on multi-FPGA systems
• Debug complex interface IP subsystems including DDR4/DDR5, LPDDR5/6/7, HBM, PCIe Gen3-6, CXL, UCIe, Ethernet, USB, AXI, and high-speed SerDes architectures
• Reproduce, analyze, and resolve critical customer escalations involving RTL issues, partitioning failures, timing violations, protocol mismatches, and hardware bring-up failures
• Collaborate directly with ProtoCompiler R&D and Product Management to validate new features, influence roadmap priorities, and represent customer requirements in product planning
• Develop and document reusable methodologies for partitioning strategies, clock architecture, debug instrumentation, verification environment adaptation, and hardware/software co-validation
• Mentor applications engineers globally, lead technical workshops and architecture reviews, and represent Synopsys at customer sites, conferences, and industry forums

• Enable customers to prototype and validate complex SoCs months earlier by solving partitioning, timing, and bring-up challenges that would otherwise block hardware availability
• Influence the ProtoCompiler roadmap and feature set based on direct engagement with the most demanding semiconductor and systems customers in the world
• Reduce critical customer escalations by building repeatable debug methodologies and training global teams on advanced troubleshooting techniques
• Accelerate adoption of HAPS prototyping platforms across AI accelerator, automotive SoC, and hyperscaler chip development programs
• Shape how Synopsys supports multi-die, chiplet, and UCIe-based architectures as the industry moves beyond monolithic SoCs
• Build long-term technical relationships with engineering leaders at strategic accounts, becoming the trusted advisor they call when deployments get hard
• Drive competitive wins by demonstrating technical depth in FPGA prototyping, emulation tradeoffs, and verification methodology that competitors cannot match

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent hands-on experience
• 10+ years working in FPGA implementation, ASIC design, ASIC verification, hardware-assisted verification, FPGA prototyping, or emulation
• Deep expertise in FPGA synthesis, place-and-route, multi-FPGA partitioning, timing closure, and constraint development using Xilinx Vivado, Intel Quartus, or equivalent tools
• Strong working knowledge of SystemVerilog, UVM, assertions, functional coverage, and verification testbench architecture
• Hands-on experience with interface IP including PCIe, DDR4/DDR5, LPDDR, Ethernet, USB, AXI, CXL, or high-speed SerDes protocols
• Proficiency in Tcl, Python, or shell scripting for automation and flow development
• Direct experience with Synopsys HAPS and ProtoCompiler is a strong plus, as is experience with ZeBu, Palladium, Protium, or Veloce emulation platforms

• You can walk into a room with a customer's architecture team, understand their SoC in an hour, and identify the three partitioning decisions that will make or break their prototype schedule
• When a PCIe link will not train or a DDR interface fails calibration, you know where to look first and how to instrument the design to prove your hypothesis
• You are comfortable presenting technical tradeoffs to VPs and engineering directors without oversimplifying the problem or losing the nuance that matters
• You do not wait for perfect information or complete documentation. You dig into logs, RTL, netlists, and hardware captures to figure out what is actually happening
• You have debugged designs using Verdi, runtime instrumentation, protocol analyzers, or assertion-based techniques and can teach others how to do the same
• You can explain why emulation and prototyping solve different problems, and you have the technical depth to back up that explanation with real architectural tradeoffs

Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.