SOC Engineering, Staff Engineer (Physical Design)

Location: Da Nang, Viet Nam

Alternate Job Titles

• Physical Design Engineer (Staff Level)
• ASIC Backend Engineer
• Physical Implementation Engineer
• RTL-to-GDSII Staff Engineer
• Physical Design Integration Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years turning RTL into silicon that actually works at the edge of what is physically possible. Not just meeting timing, actually closing complex die-to-die interfaces where a few picoseconds matter and where signal integrity is not a checkbox but the difference between a working chip and a $10M re-spin. You know that UCIe and HBM are not just acronyms, they are architectures with brutal constraints around latency, bandwidth, and power delivery that require you to think three steps ahead during floorplanning. When a timing path fails across voltage corners, you do not just throw buffers at it. You understand the tradeoff between area, power, and performance, and you make the call that gets the design to tape-out. Scripting is not a side skill for you. You automate the repetitive parts so you can focus on the hard decisions.

What You'll Be Doing

• Own RTL-to-GDSII physical implementation for UCIe IP blocks, driving synthesis, floorplanning, power grid architecture, placement, clock tree synthesis, routing, and sign-off closure at 7nm, 5nm, or 3nm
• Close timing across multiple PVT corners and operating modes, optimizing for the latency and bandwidth demands of high-speed die-to-die interfaces
• Execute physical and electrical verification using Synopsys IC Validator, resolving DRC, LVS, ERC violations and mitigating electromigration, IR-drop, and signal integrity issues
• Design and validate bump and pad ring patterns specific to die-to-die architectures, coordinating with package teams on complex routing constraints
• Build and maintain automation scripts in Python, Tcl, and Perl to streamline back-end flows and eliminate bottlenecks
• Prepare and deliver tape-out packages including GDSII databases, foundry checklists, and design documentation that meet sign-off requirements

The Impact You Will Have

• Enable Synopsys to deliver UCIe IP that meets the most aggressive performance and power targets in the industry, directly influencing chiplet adoption across AI, HPC, and data center markets
• Reduce tape-out cycle time by identifying and fixing physical design issues early, preventing costly re-spins and keeping customer programs on schedule
• Set the standard for physical design quality on advanced nodes, creating methodologies and flows that other teams across Synopsys will adopt
• Solve die-to-die interface challenges that have no textbook answers, contributing technical solutions that become part of the next generation of IP offerings
• Improve design predictability by building automation that catches timing, power, and signal integrity issues before they reach verification or silicon

What You'll Need

• Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field
• 3 to 10+ years of hands-on ASIC physical design experience with proven RTL-to-GDSII ownership, ideally including tape-outs at 7nm, 5nm, or 3nm
• Deep technical expertise in die-to-die interfaces such as UCIe, HBM, or high-speed DDR, including the timing, power, and signal integrity challenges unique to chiplet architectures
• Strong proficiency with Synopsys physical design tools including IC Compiler II or Fusion Compiler, PrimeTime for timing sign-off, and IC Validator for physical verification
• Advanced scripting skills in Tcl, Python, or Shell, with a track record of automating flows and solving complex design problems programmatically

Who You Are

• You can walk into a floorplan review, spot a power delivery problem before anyone runs IR-drop analysis, and explain exactly why it will fail at the corner that matters most
• When a timing path misses by 200ps across a die-to-die interface, you trace it back through the clock tree, the placement, and the constraints, and you know which one to fix first
• You write scripts that other engineers actually use because they solve real problems. Your Python and Tcl are clean, maintainable, and built to last beyond the current project
• You push back when a constraint does not make sense or when a design decision will create a tape-out risk three months from now

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.