Senior ASIC Digital Verification Engineer - 14705

Location: Nepean, Nepean, Canada

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

Highly motivated and innovative Senior Digital Verification engineer. Passionate about technology, driven by challenges, and eager to work on cutting-edge High-Bandwidth Memory (HBM) products. You bring a wealth of experience in digital verification, and you are proficient in System Verilog/UVM. You are a proactive problem-solver, capable of working independently and as part of a team, with the ability to network with senior internal and external personnel. Your excellent communication skills enable you to interact effectively with different design groups and customer support teams. You are self-motivated, proactive, and committed to producing high-quality designs while meeting tight deadlines.

What You’ll Be Doing:

• Verifying ASIC RTL designs at both chip and block levels
• Defining and tracking verification test plans
• Designing and writing constrained-random System Verilog testbenches using UVM (Universal Verification Methodology)
• Creating and examining Functional Coverage
• Writing System Verilog assertions
• Debugging RTL and gate-level simulation failures
• Firmware Debug
• Bug Tracking using Software Tools such as Jira
• Code Coverage Analysis

The Impact You Will Have:

• Driving the development of high-performance, low-power silicon IP solutions
• Enabling faster time-to-market for differentiated products with reduced risk
• Improving the functionality and performance of prototype test-chips through rigorous testing
• Supporting the continuous innovation and technological advancement at Synopsys

What You’ll Need:

• BSEE or MSEE with a minimum of 2+ years of digital design/verification experience
• Experience in writing testcases in System Verilog/UVM
• Experience in debugging complex testbench and design related issues
• Solid understanding of digital circuit design
• Familiarity with scripting languages (Python or Perl)
• Self-learner, independent, good organization and communication skills 

Who You Are:

• Self-motivated, independent, and resourceful in tackling technical challenges.
• Excellent organizational and communication skills, with a collaborative approach to problem-solving.
• Adaptable and eager to learn new technologies, with a strong commitment to personal and professional growth.
• Detail-oriented, analytical, and dedicated to delivering high-quality results.
• Passionate about innovation and contributing to a culture of excellence.

The Team You’ll Be A Part Of:

You will be part of an experienced mixed-signal design and verification team, targeting the next generation of HBM products. Our team is composed of veteran digital and mixed-signal engineers who are committed to delivering high-end mixed-signal designs from specification development to performing functional and performance tests on prototype test-chips. We foster a collaborative and dynamic environment that provides continuous training and professional growth opportunities.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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