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R&D Engineering Manager

Synopsys

On-site
Hyderabad, India
Full-time
Manager
10+ yrs
Salary not listedPosted 4w ago

Real job — pulled straight from Synopsys’s careers page · Verified September 10, 2026 · No reposts.

Job description

Synopsys is hiring a R&D Engineering Manager — a full-time, based in Hyderabad, India role. Apply directly on Synopsys's careers page below.

R&D Engineering, Manager

Location: Hyderabad, India

Embedded memory design

Job Description and Requirements

The Embedded Memory and Logic Team is part of Solutions Group and is responsible for standard and custom embedded SRAMs/ROMs/TCAMs development and provides both functional and physical views of memory in form of Memory compilers, A semiconductor intellectual property (IP) for the design of complex integrated circuits. The team is completely responsible for all aspects of memory development starting from Bit Cell Analysis, Architecture Design, Characterization and Verification.

 

Responsibilities

  • Manage a team and develop SRAM/Register file /TCAM /ROM architectures and circuit implementation techniques.
  • Schematic entry, simulation of major blocks, layout planning, layout supervision and interface with CAD team for full verification and model generation.
  • Designing and implementing optimum low-power and area-efficient embedded memory (SRAM, register files, etc.) circuits and architectures.
  • Learn and apply skills in memory compilers having Transistor level circuit Design.
  • Resolves a wide range of issues in creative ways
  • Inter-team interaction 
  • Customer focus 
  • Frequently networks with senior internal and external personnel in own area of expertise
  • Experience of FinFet Technology for Memory Design
  • Can coordinate, facilitate, and monitor the daily activities of a small to large group of support resources within their section or project team 
  • With minimal supervision, prioritizes workload to successfully manage multiple tasks and responsibilities
  • Proactively addresses and communicates issues impacting productivity

 

As a Manager, the individual will be involved in challenging projects and drive it to completion in record time. 

You will quickly ramp on the existing flow, understand the challenges, and produce the work plan. 

Your expertise in deep submicron technology and Finfet, SRAM design, processor design, Digital design flow and teamwork skills will be highly leveraged to guide activity across the entire cross-discipline, multi-site team.

You will work with others to identify the issues, get buy-in on proposed solutions, and implement the solutions in time for the team to execute to schedule.

 

Skills/Experience:

  • 10yrs+ Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation.
  • BE/B.Tech/ME/M.Tech/MS in Electrical & Electronics Engineering from premium institute/university 
  • Deep understanding of SRAM/Register File architectures and advanced custom circuit implementations.
  • Direct experience with the most advanced technology nodes. Familiarity with variation-aware design in nanometre technology nodes
  • Mastery in scripting using Perl, python for automation 

 

Fundamentals:

  • Understanding of RC circuit of 1st and 2nd order.
  • Basics of Digital design (realization of Boolean function using Gates, Mux etc)
  • Fundamentals of Transfer function and its analysis for stability etc.
  • Strong CMOS fundamentals
  • Knowledge of CMOS fabrication
  • Good digital design knowledge
  • Exposure to basic Analog fundamentals

 

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

 

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Frequently asked questions

What skills are required for R&D Engineering Manager at Synopsys?

The required skills for R&D Engineering Manager at Synopsys include: Perl, Python.

What is the seniority level for R&D Engineering Manager at Synopsys?

R&D Engineering Manager at Synopsys is a Manager level position.

How do I apply for R&D Engineering Manager at Synopsys?

You can view the full description and apply for R&D Engineering Manager at Synopsys on EchoJobs: https://echojobs.io/job/synopsys-r-d-engineering-manager-jo39r.