Physical Design Applications Engineer

Location: Sunnyvale, California, United States

At Synopsys, we drive the innovations that shape the way the world connects and computes. Our technology powers cutting-edge silicon in applications from mobile and AI to autonomous systems and advanced computing. Join us to help customers achieve breakthrough performance using our leading EDA tool suite. 

We are seeking a Physical Design Engineer with strong technical skills in digital implementation and optimization. In this role you will work with engineering teams and customers to deliver solutions that drive timing closure, power and area optimization, and robust RTL-to-GDS flows using Synopsys tools. 

You Are

You are an ASIC/physical design engineer with 2-4 years of hands-on experience in digital implementation flows. You understand full RTL-to-GDS design flows and are comfortable applying state-of-the-art methodologies to achieve timing closure and quality signoff. You have solid scripting skills to automate flows and customize solutions, and you communicate clearly with internal teams and customers to solve complex design challenges. 

What You’ll Be Doing

• Execute RTL-to-GDSII digital implementation flows, including logic synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off quality closure.
• Work with customers and internal teams to troubleshoot and optimize implementation challenges, propose solutions, and deliver highly-tuned PPA results.
• Utilize Synopsys tools such as Fusion Compiler, PrimeTime, and DSO.ai/FusionAI in digital implementation and static timing analysis.
• Develop and enhance automation scripts and flows using TCL, Python, Perl, or other scripting languages.
• Perform static timing analysis (STA), debug timing violations, and implement ECOs to improve performance and timing closure.
• Drive DRC/LVS/Signoff quality closures at advanced technology nodes.
• Collaborate with customers, product teams, and research groups to share best practices and feedback to improve tool flows.  

What You’ll Need

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.
• 2–4 years of hands-on experience in digital physical design or backend implementation.
• Experience with full RTL-to-GDS flows, including place & route methodologies, STA, timing closure, and signoff strategies.
• Proficiency with Synopsys tools such as Fusion Compiler, PrimeTime, and familiarity with AI-assisted optimization tools (e.g., DSO.ai/FusionAI) is highly desirable.
• Solid scripting skills in TCL, Python, Perl, or equivalent for flow automation.
• Strong analytical ability to dissect complex timing, PPA, and design challenges.
• Familiarity with unix/linux environments and engineering workflows.
• Excellent communication skills and ability to work in collaborative team and customer-facing environments.  

Who You Are

• A proactive self-starter who takes ownership of technical solutions and delivery.
• Comfortable interfacing with customers and internal teams to understand requirements and deliver effective outcomes.
• Able to adapt to evolving methodologies and rapidly learn emerging tool capabilities in EDA.
• Detail-oriented and organized, capable of balancing multiple priorities in a fast-paced environment.  

The Team You’ll Be Part Of

Join a dynamic Applications Engineering team dedicated to customer success and powerful EDA solutions. You’ll work closely with fellow engineers, researchers, and tool developers to enable high-performance physical design solutions and push the boundaries of what’s possible in semiconductor design.