Principal Engineer, PCIe System Architect
Real job — pulled straight from Synopsys’s careers page · Verified August 26, 2026 · No reposts.
Job description
Synopsys is hiring a Principal Engineer, PCIe System Architect — a full-time, based in Sunnyvale, CA role. Apply directly on Synopsys's careers page below.
PCIe System Architect/ Principal Engineer-18290
Location: Sunnyvale, California, United States
We Are
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are
You are PCIe/CXL System Architecture Specialist who can work directly with customer architects to close real system-level design decisions.
You are comfortable discussing SoC integration, IP configuration, performance considerations, validation, compliance, and interoperability topics. You can help customers evaluate technical trade-offs and guide them toward practical architecture decisions.
This is a customer-facing technical role. You will help customers integrate PCIe/CXL controller IP into complex SoCs, identify key requirements or gaps, and translate customer feedback into actionable input for Synopsys Product Management, R&D, and roadmap planning.
What You’ll Be Doing
- Own the technical architecture engagement for PCIe/CXL controller IP with strategic customers, from early platform requirements through architecture closure and initial deployment readiness.
- Work with customer architects and engineering teams to define suitable PCIe/CXL subsystem configurations for advanced SoC platforms.
- Analyze system-level trade-offs related to performance, power, reliability, validation, compliance, and interoperability.
- Translate customer platform requirements and integration constraints into clear feedback for Synopsys Product Management, R&D, and roadmap planning.
- Support technical closure of design wins by providing architecture guidance, configuration recommendations and competitive positioning.
- Develop reusable technical material, application notes, and customer-facing guidance based on real engagement experience.
- Train FAEs and customer teams on PCIe/CXL architecture, integration trade-offs, validation expectations, and deployment best practices.
What You’ll Need
- Bachelors and/or Masters Degree in Electrical and/or Electronic Engineering, Computer Engineering or Computer Science
- 10+ years of experience in PCIe/CXL architecture, SoC integration, silicon validation, systems engineering, applications engineering, or customer-facing technical leadership.
- Solid understanding of PCIe and/or CXL controller IP, including protocol concepts, configuration, integration, validation, compliance, or interoperability.
- Good system-level understanding of SoC integration and ability to reason through performance, power, reliability, validation, and software/firmware trade-offs.
- Experience engaging directly with customer architects, design teams, validation teams, and technical decision-makers.
- Ability to translate ambiguous customer requirements into clear technical recommendations, product feedback, and closure plans.
- Strong technical communication skills, including clear written analysis, structured trade-off explanation, and ability to align customer, sales, product, and engineering teams.
The Impact You Will Have
- Improve the quality of PCIe/CXL design wins by ensuring customer architectures are technically sound before commitment.
- Strengthen Synopsys PCIe/CXL roadmap by feeding real customer system requirements into product planning and R&D execution.
- Reduce customer integration risk by identifying architecture, firmware, validation, compliance, and interoperability issues early.
- Help establish Synopsys as a trusted technical partner for next-generation AI, HPC, storage, networking, and CXL-enabled platforms.
Nice to Have
- Experience with Linux, firmware bring-up, or software-driven debug of PCIe/CXL subsystems.
- Familiarity with advanced SoC architectures used in AI, HPC, storage, networking, or compute platforms.
- Participation in PCI-SIG, CXL Consortium, or related ecosystem/standards activities.
- Knowledge of advanced topics such as coherency, virtualization, RAS, memory expansion, or CXL-based platform architectures.
The Team You’ll be a Part Of
You will be part of our IP high-performance computing applications engineering team, a group of dedicated professionals who are passionate about technology and innovation. The team focuses on helping customers integrate more capabilities into SoCs faster, working collaboratively across geographic and organizational boundaries to drive revenue growth and accelerate business closure.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Inclusion and Diversity
Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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Frequently asked questions
What skills are required for Principal Engineer, PCIe System Architect at Synopsys?
The required skills for Principal Engineer, PCIe System Architect at Synopsys include: PCIe, Linux.
What is the seniority level for Principal Engineer, PCIe System Architect at Synopsys?
Principal Engineer, PCIe System Architect at Synopsys is a Principal / Senior level position.
How do I apply for Principal Engineer, PCIe System Architect at Synopsys?
You can view the full description and apply for Principal Engineer, PCIe System Architect at Synopsys on EchoJobs: https://echojobs.io/job/synopsys-pcie-system-architect-principal-engineer-18290-n5aei.