Layout Design, Sr Engineer

Location: Bengaluru, India

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and detail-oriented engineer ready to make a significant impact in the world of silicon IP design. With a strong foundation in layout development and a keen interest in advanced process technologies, you thrive when working on challenging projects that push the boundaries of innovation. You bring a solid understanding of deep submicron effects and are adept at applying layout techniques in CMOS, FinFET, and GAA processes, especially in nodes 7nm and below. Your hands-on experience in floorplanning, routing, and physical verifications has equipped you with the skills to deliver high-quality layouts that meet stringent industry standards. You are committed to continuous learning and adapt quickly to new technologies and methodologies. You believe in the power of collaboration and actively foster accountability and ownership within teams. Your communication skills—both written and verbal—allow you to articulate complex technical concepts clearly, making you a valued contributor and mentor. You embrace diversity and inclusion, recognizing that varied perspectives drive innovation and excellence. If you're excited about working on next-generation DDR/HBM/UCIe PHY IPs and contributing to the development of differentiated products, Synopsys offers the perfect environment for your growth, creativity, and impact.

What You’ll Be Doing:

• Developing layouts for cutting-edge DDR, HBM, and UCIe PHY IPs using advanced process technologies.
• Executing layout floor planning, routing, and optimizing physical design to meet quality and performance requirements.
• Performing rigorous physical verification checks including DRC, LVS, ERC, Antenna, and layout matching techniques.
• Applying deep submicron knowledge to address effects and challenges in CMOS, FinFET, and GAA nodes (7nm and below).
• Collaborating with cross-functional teams to ensure seamless integration and delivery of IP blocks.
• Generating LEF files and supporting DFM, ESD, latch-up, EMIR analysis, and layout documentation.
• Contributing to process improvements and advocating best practices in layout development.

The Impact You Will Have:

• Accelerating the development and integration of high-performance silicon IPs for next-generation SoCs.
• Enabling customers to bring differentiated products to market faster with reduced risk.
• Enhancing the quality, reliability, and manufacturability of Synopsys PHY IPs through meticulous layout design and verification.
• Driving innovation in advanced process technologies, supporting industry-leading features and performance.
• Fostering a collaborative and inclusive culture, empowering teams to achieve ambitious goals.
• Contributing to Synopsys’ reputation as a global leader in IP design and chip development.

What You’ll Need:

• BTech/MTech degree in Electronics, Electrical, or related field.
• Minimum 2+ years of hands-on experience in layout development and physical verification for advanced nodes.
• Proficiency in DRC, LVS, ERC, Antenna checks, and layout matching techniques.
• Strong understanding of deep submicron effects, floorplanning, and process technologies (CMOS, FinFET, GAA—7nm and below).
• Experience with ESD, latch-up, EMIR, DFM, and LEF generation.
• Familiarity with industry-standard layout tools and methodologies.

Who You Are:

• Analytical thinker with exceptional problem-solving and debugging skills.
• Collaborative team player who fosters accountability and ownership.
• Effective communicator with strong written and verbal skills.
• Adaptable, self-driven, and eager to learn new technologies.
• Committed to inclusion, diversity, and creating a positive workplace culture.

The Team You’ll Be A Part Of:

You will join a dynamic and innovative Silicon IP layout engineering team based in Bangalore, focused on developing next-generation DDR, HBM, and UCIe PHY IPs. The team collaborates closely with architects, verification engineers, and product managers to deliver high-quality, differentiated IP solutions for global customers. Your contributions will be integral to driving technical excellence and shaping the future of chip design.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.