Layout Design Senior Engineer- IO SerDes

Location: Bengaluru, India

IO Layout Senior Engineer - SerDes

We Are:
 At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are: 

You are a seasoned professional with a deep understanding of Analog and Mixed Signal Circuit Layout. With a minimum of 3 years of experience, you bring a strong background in transistor-level analog and mixed-signal layout design. You possess extensive knowledge in CMOS and FINFET technologies, and your expertise in semiconductor device physics sets you apart. Your problem-solving skills are top-notch, and you are detail-oriented, self-directed, and passionate about learning new techniques. You are adept at communicating effectively with cross-functional teams to ensure successful project execution. You thrive in a dynamic environment and are excited about the opportunity to contribute to cutting-edge technology that drives the future.

What You’ll Be Doing:

• Plan, estimate area/time, schedule, delegate, and execute tasks to meet project milestones in a multi-project environment.
• Collaborate with cross-functional teams to ensure successful project execution.
• Create and review layout documents to ensure they meet quality standards and are delivered on time.
• Support the team in troubleshoot physical verification issues to achieve clean and desired results
• Device level floorplan, placement, routing, and physical verification of all critical high-speed blocks
• Design and development of transistor-level Analog and mixed-signal layout as per project needs

The Impact You Will Have: 

• You will drive the Layout design of the project from Floorplan, design and development till the project release.
• You will drive the Layout design of the project from Floorplan till the project release and lead the project throughout the entire design and development phase.
• Strong Knowledge and experience in layout design of high-speed blocks in latest Tech Nodes (2nm, 3nm, 5nm)
• You will drive the design and development of high-quality analog and mixed-signal layouts.
• Your expertise will ensure the successful implementation of CMOS and FINFET technologies.
• Through effective troubleshooting, you will contribute to achieving clean physical verification results.
• Your attention to detail will ensure that layout documents meet quality standards and deadlines.
• By managing project schedules and milestones, you will help deliver projects on time.
• Your collaboration with cross-functional teams will enhance project success and innovation

What You’ll Need:

• Bachelor's or master's degree in electrical engineering or a related field.
• Minimum 3+ years of experience in Analog and Mixed Signal Circuit Layout.
• Proficiency in Analog Layout Flow from device placement to GDS release.
• Strong knowledge of CMOS and FINFET technologies and semiconductor device physics.
• Experience with EDA tools for custom mixed-signal layout flows.
• Understanding of CMOS fabrication technology and deep sub-micron effects on layout.
• Knowledge of electro-migration, reliability concepts, and ESD/LUP concepts as applied to layout.
• Passion for learning and exploring new techniques.

Who You Are:.

• Detail-oriented and committed to delivering high-quality results.
• Innovative and capable of driving technological advancements.
• Collaborative and able to work effectively with cross-functional teams.
• A problem-solver with strong analytical skills.

The Team You’ll Be a Part Of:
 You will be part of a dynamic and innovative layout design team focused on creating high-performance analog and mixed signal layouts. The team is dedicated to excellence and continuous improvement, working collaboratively to achieve the organization's goals.