We Are:

At Synopsys, we drive the innovations that shape how we live and connect. Our technology is central to the Era of Pervasive Intelligence — from self-driving cars to learning machines — and we lead in chip design, verification, and IP integration that power high-performance silicon and software.

Within our HPC Controller IP organization, the mid-end team is the bridge between RTL design and physical implementation. We build the flows, automation, and quality checks that synthesize, verify, package, and release complex soft IP at scale — and we hand physical-design teams inputs that are clean, constrained, and implementation-ready.

You Are:

A motivated mid-end engineer with a solid grasp of ASIC design and verification flows, and genuine enthusiasm for automation, flow robustness, and using AI to raise engineering productivity, debug speed, and quality of results. You partner naturally with RTL designers to understand design intent, turn their outputs into physical-design-ready inputs, and collaborate across verification, DFT, physical design, methodology, and tooling teams. You communicate clearly, take ownership, and let data guide your decisions.

What You’ll Be Doing:

• Develop, run, and support mid-end flows spanning synthesis, DFT, static checking (SpyGlass), formal equivalence, power analysis, and related quality gates.
• Convert RTL outputs into clean, constrained, implementation-ready inputs for physical design.
• Build and maintainTcl-based automation, dashboards, and project infrastructure — and apply AI to accelerate the work (e.g., triaging flow logs, summarizingQoRtrends, drafting and refactoring scripts).
• Debug flow failures end to end:analyzereports, isolate root cause, and drive issues to closure with design, verification, DFT, and implementation teams.
• Improve documentation, handoff criteria, and reusable collateral so execution stays consistent across IP programs.

The Impact You Will Have:

• Higher-quality RTL-to-physical-designhandoffs and lower implementation risk.
• Faster, more scalable execution through stronger automation and AI-enabled analysis.
• Synthesis, DFT, static, formal, and power issues caught earlier in the cycle.
• Tighter collaboration across the RTL-to-implementation chain.
• Robust, implementation-ready soft IP shipped with clear constraints, checks, and release collateral.

What You’ll Need(Core):

• Working knowledge of ASIC design, verification, and mid-end development flows, typically gained through 5+ years of relevant experience or equivalent project work.
• Hands-on synthesis experience, with the ability toanalyzeand resolve synthesis issues.
• StrongTclscripting skills and a practical, automation-first mindset.
• Familiarity with at least two of: DFT concepts, static checking (SpyGlassor equivalent), formal equivalence (e.g., Formality), or power analysis — and willingness to grow across the rest.
• Ability to use AI tools effectively to accelerate debugging, summarize results, and improve scripts and flows.
• Strong analytical, problem-solving, communication, and documentation skills.
• BS/MS in Electrical/Computer Engineering or equivalent experience.

Nice to have :

• Experience across the full mid-end set: DFT,SpyGlass, Formality, and power analysis.
• IP development methodologies, IP packaging, or reusable IP delivery / release collateral.
• Hands-on with Synopsys tools such as Fusion Compiler and VCSpyGlass.

Who You Are:

• Proactive, curious, and adaptable.
• Collaborative and ethical.
• Flow-oriented, AI-aware, and quality focused.
• Resilient and resultsoriented.

The Team You’ll Be A Part Of:

You’ll work with a high-impact High-Performance-Compute team focused on delivering complex IP to the marketplace. You will collaborate across RTL design, verification, DFT, physical design, methodology, and project infrastructure teams to improve mid-end readiness and enable predictable downstream implementation.

Rewards and Benefits: