
Real job — pulled straight from Synopsys’s careers page · Verified September 10, 2026 · No reposts.
Job description
Synopsys is hiring a Principal Engineer, DDR/LPDDR IP Design — a full-time, based in Wuhan, China role. Apply directly on Synopsys's careers page below.
DDR/LPDDR IP Design Principal Engineer
Location: Wuhan, China
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Seeking a highly motivated and innovative senior engineer with wide-spectrum knowledge of generic ASIC design methodology, and simulation/silicon debug skills.
The candidate would be working as part of a highly experienced DDR/LPDDR design and verification team, targeting the current and next generation technology. Theoretical and practical background in DDR or LPDDR is a solid plus.
The position offers an excellent opportunity to work with a professional team of digital and mixed-signal engineers responsible for delivering high-end designs and supporting DDR/LPDDR products.
Key Qualifications
- BSEE in EE with 12+ years of digital design experience or MSEE with 9+ years of relevant experience
- Work on digital design based on predefined RTL coding style include Verilog and System Verilog, clean RTL check violations in lint, CDC, DFT and synthesis
- Solid Debugging skills and ability to root cause issues include both simulation and silicon
- Good knowledge of SNPS EDA tools like VCS, Verdi, Spyglass, DC, Formality
- Good communication skills for interacting between different design groups and customer support teams are required
Preferred Experience
- Has strong desire to learn and explore new technologies
- Demonstrates good analysis and problem-solving skills
- Knowledge in interface technologies such as DDR, HBM, UCIe is a plus
- Scripting experience in Shell, Perl, Python and TCL is a plus
- Knowledge of analogic circuit is a plus
- Interacting with Application Engineers for customer support
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Frequently asked questions
What skills are required for Principal Engineer, DDR/LPDDR IP Design at Synopsys?
The required skills for Principal Engineer, DDR/LPDDR IP Design at Synopsys include: Verilog, SystemVerilog, Shell, Perl, Python.
What is the seniority level for Principal Engineer, DDR/LPDDR IP Design at Synopsys?
Principal Engineer, DDR/LPDDR IP Design at Synopsys is a Principal level position.
How do I apply for Principal Engineer, DDR/LPDDR IP Design at Synopsys?
You can view the full description and apply for Principal Engineer, DDR/LPDDR IP Design at Synopsys on EchoJobs: https://echojobs.io/job/synopsys-ddr-lpddr-ip-design-principal-engineer-wfxgz.