ASIC Physical Design, Sr Engineer

Location: Bengaluru, India

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and resourceful ASIC Physical Design engineer ready to tackle the complex challenges of next-generation silicon. With a strong foundation in VLSI concepts, you thrive in dynamic, collaborative environments and are motivated by the opportunity to learn and grow. You are adept at communicating technical ideas, whether collaborating with teammates in Bangalore or interacting with colleagues in the US. Your attention to detail and commitment to quality ensure your designs meet stringent performance and power requirements. You bring a proactive attitude, always seeking new ways to optimize and innovate, and you embrace challenges such as achieving timing closure at GHz frequencies and integrating mixed-signal macros. Your experience with DDR IP or high-speed interface implementations is a strong asset, and you are eager to contribute to world-class products at the forefront of semiconductor technology. You value teamwork, knowledge sharing, and continuous improvement, recognizing that the best solutions are built together. If you are looking to make an impact at the leading edge of physical design, Synopsys is the place for you.

What You’ll Be Doing:

• Implement and integrate state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).
• Drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability.
• Collaborate with local and US-based teams, engaging in daily technical discussions to align on project goals and challenges.
• Integrate mixed-signal hard macro IPs and address unique integration requirements with innovative solutions.
• Design and build efficient clock trees, focusing on tight skew balancing and robust clock distribution.
• Participate in design reviews, debug issues, and contribute to continuous improvement of physical design methodologies.
• Support the implementation of best practices in floorplanning, placement, routing, and power optimization.
• Mentor junior engineers and contribute to team knowledge sharing initiatives.

The Impact You Will Have:

• Enable delivery of high-performance DDR IPs that power next-generation consumer and enterprise products.
• Advance Synopsys’ leadership in IP implementation at cutting-edge technology nodes.
• Champion best-in-class timing closure and integration practices, raising the bar for design excellence.
• Facilitate seamless cross-site collaboration, ensuring global project success.
• Drive innovation in clock tree synthesis and mixed-signal integration, contributing to differentiated product offerings.
• Accelerate time-to-market for customers by delivering robust, silicon-proven IP solutions.

What You’ll Need:

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or related field.
• 3+ years of experience in ASIC physical design, especially at advanced technology nodes (10nm, 7nm, 6nm or below).
• Proficiency with physical design tools (such as Synopsys ICC2, PrimeTime, StarRC, etc.).
• Solid understanding of timing closure, clock tree synthesis, and skew balancing for high-frequency designs.
• Experience with DDR interface implementation and/or mixed-signal IP integration is highly desirable.
• Familiarity with scripting languages (Tcl, Perl, Python) for automation and workflow optimization.
• Strong analytical and debugging skills for addressing complex design challenges.

Who You Are:

• Collaborative team player who values open communication and knowledge sharing.
• Detail-oriented with a commitment to quality and continuous improvement.
• Self-motivated, proactive, and eager to take initiative in solving technical challenges.
• Adaptable and resilient in fast-paced, evolving environments.
• Effective communicator, able to articulate complex ideas to diverse audiences.

The Team You’ll Be A Part Of:

You’ll join the Synopsys DDR IP implementation team, a group of passionate engineers focused on delivering world-class memory interface solutions at the leading edge of semiconductor technology. The team fosters a culture of innovation, technical excellence, and collaboration, working closely with global counterparts to achieve ambitious project goals. Together, you’ll help shape the future of high-performance silicon and enable the next wave of intelligent systems.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.