ASIC Front-end Implementation Staff Engineer

Location: Bengaluru, India

ASIC Front-end Implementation Staff Engineer 

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and detail-oriented engineer with a drive to push the boundaries of what’s possible in semiconductor technology. With 4-8 years of hands-on experience in ASIC or SoC front-end implementation, you thrive in complex design environments where your expertise in RTL-to-netlist flows, synthesis, and verification is highly valued. You’re adept at collaborating with cross-functional teams, communicating technical concepts clearly, and resolving challenges with innovative solutions. Your foundation in electronics or electrical engineering, coupled with experience in scripting and automation, enables you to optimize for power, performance, and area, ensuring high-quality IP delivery. You are committed to continuous learning, eager to adopt new tools and methodologies, and value diversity and inclusion as essential elements for growth and creativity. Your proactive approach, attention to detail, and resilience in the face of technical challenges make you a trusted contributor and a supportive teammate. If you’re ready to shape the next generation of Ethernet IP solutions and be part of a dynamic global team, you’ll find your next rewarding challenge at Synopsys.

What You’ll Be Doing:

• Performing RTL lint checks and collaborating with design engineers to resolve issues and create effective waivers.
• Analyzing and signing off on Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC), working closely with RTL teams to understand and optimize domain architectures.
• Executing RTL DFT (Design for Test) analysis and enhancing DFT coverage for stuck-at faults and other failure modes.
• Developing and managing timing constraints for RTL synthesis and static timing analysis (STA) to ensure robust, high-performance IP delivery.
• Specifying power intent in UPF for multi-voltage designs, performing detailed power estimations, and identifying opportunities for power reduction at both RTL and gate levels.
• Running formal verification between RTL and gate-level netlists, debugging logic equivalency issues, and ensuring design integrity.
• Leading logic and physical synthesis using advanced optimization techniques, generating optimized gate-level netlists, and resolving timing, area, and congestion challenges.
• Developing automation scripts and methodologies for front-end tools, streamlining workflows, and enhancing overall productivity.
• Collaborating with RTL, DV, FPGA validation, and physical design engineers to facilitate seamless handoffs and support cross-functional development efforts.

The Impact You Will Have:

• Accelerating the delivery of high-performance Ethernet IP solutions for next-generation networking applications.
• Enabling customers to bring differentiated products to market quickly and with reduced risk by ensuring IP quality and reliability.
• Driving improvements in power, performance, and area, directly influencing the competitiveness of Synopsys’ IP portfolio.
• Streamlining and automating front-end implementation flows, setting new standards for efficiency and scalability.
• Facilitating effective cross-team collaboration, ensuring smooth integration between design, verification, and physical implementation groups.
• Contributing to the advancement of best practices and methodologies, fostering a culture of continuous improvement and innovation.
• Mentoring and guiding junior engineers, sharing knowledge, and strengthening the team’s technical capabilities.

What You’ll Need:

• Bachelor’s or Master’s degree in electronics or electrical engineering (or equivalent) from a reputed institution.
• 4-8 years of experience in ASIC/SoC/IP front-end implementation, especially in RTL-to-netlist flows.
• Expertise in RTL design using Verilog or SystemVerilog, and familiarity with CDC, RDC, and logic equivalency checking (LEC).
• Hands-on experience with RTL synthesis, design optimization for power, performance, and area (PPA), and low-power concepts (UPF/CPF).
• Strong proficiency in industry-standard EDA tools such as Synopsys SpyGlass, Fusion Compiler, Design Compiler, PrimeTime, Formality, or equivalent.
• Working knowledge of technology files, standard cell libraries, SRAM memories, and physical design data formats (liberty, lef, def, gds, Milkyway, NDM).
• Advanced scripting skills in TCL, Perl, or Python for automation and productivity improvement.

Who You Are:

• Analytical thinker with strong problem-solving abilities and attention to detail.
• Collaborative team player who communicates effectively across functions and cultures.
• Self-motivated and proactive, always looking for ways to improve processes and outcomes.
• Adaptable and resilient in fast-paced, evolving environments.
• Committed to fostering diversity, equity, and inclusion in the workplace.

The Team You’ll Be A Part Of:

You’ll join the Synopsys Ethernet IP Solutions Group in Bangalore, a talented and diverse team dedicated to developing Ethernet MAC controllers across a range of speeds (QoS/1G/10G/25G/100G/200G/400G/800G). The team collaborates closely with global design, validation, and physical implementation experts, leveraging Synopsys’ world-leading IP portfolio to deliver innovative, high-quality solutions for customers worldwide.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.