ASIC Digital Design, Sr Staff/Principal Engineer - DDR

Location: Bengaluru, India

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and accomplished digital design engineer with an unyielding drive for excellence. You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems. With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM. Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.

You are adept at translating functional specifications into detailed micro-architecture and design documents, always ensuring clarity and precision. Your technical toolkit includes mastery of Verilog/SystemVerilog, and you are well-versed in industry-standard flows encompassing linting, CDC analysis, synthesis, and static timing. You’re not just a Sr technical expert; you are a proactive communicator, an enthusiastic collaborator, and a natural problem solver who takes initiative and ownership of deliverables. Your ability to adapt to a global, multi-site team environment is matched only by your commitment to continuous learning and professional growth. If you’re ready to take on a pivotal role in shaping next-generation silicon IP, Synopsys is where your aspirations and impact can soar.

What You’ll Be Doing:

• Lead and Drive all aspects of complete IP Design execution from start to end.
• Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.
• Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.
• Contributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development. 
• Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.
• Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.
• Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.
• Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.

The Impact You Will Have:

• Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.
• Elevating Synopsys’ reputation for technical excellence and innovation in the IP design space.
• Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.
• Enabling customers to achieve faster time-to-market and superior silicon performance.
• Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.
• Driving continuous improvement in design methodologies, enhancing efficiency and product quality.
• Supporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.
• 10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.
• Past experience of leading IP deign projects, team.
• In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.
• Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.
• Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).
• Familiarity with scripting languages such as Perl or Shell—an advantage.
• Demonstrated ability to technically lead or mentor small teams of engineers.

Who You Are:

• A collaborative team player who thrives in a multi-site, multicultural environment.
• An effective communicator, able to translate complex technical concepts for diverse audiences.
• A proactive problem-solver with strong analytical and troubleshooting skills.
• Self-motivated, showing high initiative and ownership of responsibilities.
• Adaptable and eager to learn, always seeking opportunities for personal and professional growth.
• Committed to fostering a positive, inclusive, and innovative team culture.

The Team You’ll Be A Part Of:

You will join the R&D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores. As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design. The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.