ASIC Digital Design, Sr Staff Engineer

Location: Yerevan, Armenia

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You bring extensive ASIC digital design experience with a track record of delivering production RTL for complex semiconductor IP. Your expertise encompasses timing closure, power optimization, and design quality across advanced process nodes.

You work effectively across organizational boundaries, collaborating with architecture, verification, and physical design teams. You manage technical tradeoffs systematically, balancing performance, area, and power requirements while maintaining schedule commitments. When faced with evolving specifications, you provide data-driven analysis and practical solutions. At Synopsys, you will contribute to UCIe Controller IP that powers HPC applications in production silicon worldwide.

What You'll Be Doing

* Design RTL modules for UCIe Controller IP from microarchitecture through synthesis-ready implementation

* Optimize designs to meet timing, power, and area targets across multiple process nodes

* Develop Python/tcl/perl automation for design generation and flow integration

* Collaborate with cross-functional teams to resolve timing and power challenges

* Contribute to design reviews and methodology development

The Impact You Will Have

* Your designs will enable UCIe IP deployed in high-volume HPC, automotive, and AI products

* You will contribute to a solid revenue-generating product line for Synopsys

* Your work will define performance characteristics for customer systems-on-chip

* Your automation will improve design efficiency across the engineering team

* Your expertise will influence architectural decisions for future products

What You'll Need

* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field

* 8+ years of ASIC digital design experience with RTL ownership in production silicon

* Expert Verilog proficiency for timing-critical designs

* Strong Python/Tcl/Perl scripting skills for design automation

* Deep knowledge of synthesis, timing analysis, and power optimization

* Experience with Controller IP or high-speed interfaces is preferred

Who You Are

* You understand how RTL structure affects timing and power outcomes

* You communicate effectively across technical disciplines

* You produce maintainable code that supports collaboration

* You identify process improvements proactively

* You resolve technical issues through systematic analysis

The Team You'll Be Part Of

You will join the team responsible for front-end design, verification and release of UCIe Controller IP. This core product generates significant revenue and enables critical functionality in customer designs across HPC, automotive, and AI markets.