ASIC Digital Design, Principal Engineer-14687

Location: Mississauga, Mississauga, Canada

We are open to hiring in multiple locations- Mississauga (Preferred), Open to Ottawa, Markham. 

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

As a Principal ASIC Digital Design Engineer, you are a trailblazer who thrives in dynamic environments and is passionate about pushing the boundaries of semiconductor technology. You bring a deep understanding of digital design methodologies, paired with a creative approach to problem-solving and a tenacious drive to deliver robust solutions. Your expertise in high-speed serializer and data recovery circuits positions you as a key contributor to the next generation of PAM-based SerDes products. With a proven track record of leading complex projects, you are comfortable navigating ambiguity, balancing high-quality design with tight deadlines, and exercising independent judgment in selecting methods and techniques to achieve project goals.
You are not only technically proficient in RTL coding and digital verification, but you also bring a practical understanding of synthesis flows, DFT, and production testing. Your scripting skills in Shell, Perl, Python, and TCL enable you to automate tasks and streamline development workflows. You are motivated by continuous learning and embrace challenges as opportunities to innovate and grow. Ultimately, you are driven to make a lasting impact in the semiconductor industry by delivering high-performance, reliable mixed-signal designs that power tomorrow’s technology.

What You’ll Be Doing:

• Designing and verifying advanced digital circuits for PAM-based SerDes PHY IP, ensuring robust and high-performance mixed-signal solutions.
• Developing RTL code, modeling analog blocks, and crafting complex system-level testbenches in Verilog to validate functionality and performance.
• Defining synthesis constraints, resolving timing and gate-level simulation issues, and ensuring seamless integration into production flows.
• Addressing Clock/Reset domain crossing challenges, utilizing CDC/RDC tools to evaluate and resolve violations.
• Enhancing and maintaining existing SERDES PHY IPs to support multiple communication protocols and evolving customer requirements.
• Collaborating with Application Engineers, Analog, and P&R teams to resolve technical issues, provide customer support, and ensure successful product deployment.
• Mentoring junior engineers, fostering knowledge sharing and contributing to a culture of innovation and continuous improvement.

The Impact You Will Have:

• Drive the development of next-generation SerDes solutions, powering high-speed data transmission in cutting-edge applications.
• Enable customers to achieve superior performance and reliability in their semiconductor products through innovative digital design.
• Contribute to Synopsys’ leadership in mixed-signal IP development, expanding our portfolio and market reach.
• Accelerate product delivery timelines by optimizing digital workflows and resolving complex technical challenges.
• Shape industry standards for digital signal processing and data recovery circuits, influencing future technology directions.
• Enhance team capabilities by mentoring peers and sharing expertise, strengthening our collaborative engineering culture.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering (BSEE or MSEE) with at least 10 years of industry experience in digital design and verification.
• Must be familiar with Verilog and VCS. Good knowledge of back-end synthesis tools DC/PT is required
• Must have knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows
• Scripting experience in Shell, Perl, Python and TCL is a plus
• Good theoretical and practical understanding of digital signal processing and data recovery circuits is a strong plus

Preferred Experience

• RTL coding, modeling of analog blocks, and writing complex system-level test-benches in Verilog
• Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures
• Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools
• Enhancing and maintaining existing SERDES PHY IPs supporting multiple protocols
• Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams

Who You Are:

• Self-motivated, proactive, and able to deliver high-quality results under tight deadlines.
• Creative problem solver, exercising independent judgment and resourcefulness.
• Effective communicator, skilled at collaborating with diverse technical teams and customers.
• Mentor and team player, eager to guide junior engineers and contribute to a positive team environment.
• Adaptable and resilient, thriving in a rapidly evolving technological landscape.

The Team You’ll Be A Part Of:

You will join a highly experienced mixed-signal design and verification team, focused on advancing the capabilities of PAM-based SerDes products. The team is comprised of digital and mixed-signal engineers who work collaboratively from specification development through prototype testing. This dynamic group values innovation, continuous learning, and technical excellence, providing you with opportunities for initial and ongoing training from industry-leading experts.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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