Real job — pulled straight from Synopsys’s careers page · Verified September 17, 2026 · No reposts.
Job description
Synopsys is hiring a Principal ASIC Design Verification Engineer — a full-time, based in Hsinchu, Taiwan role. Apply directly on Synopsys's careers page below.
ASIC Design Verification Engineer, Principal
Location: Hsinchu, Taiwan
About Synopsys:
At Synopsys, we drive the innovations that shape how we live and work—self-driving cars, artificial intelligence, cloud computing, 5G, and the Internet of Things. As a leader in advanced chip design and software security technologies, we empower the Era of Smart Everything. If you share our passion for innovation, we invite you to join our team.
About Silicon IP:
Our Silicon IP business enables customers to integrate advanced capabilities into SoCs quickly and efficiently. We offer the industry’s broadest portfolio of silicon IP, including logic, memory, interfaces, analog, security, and embedded processors. Our solutions help customers meet unique application requirements and accelerate differentiated product delivery with reduced risk.
Job Responsibilities:
- Develop verification strategies and plans for ASIC/SoC projects
- Define and implement testbench architecture and methodologies
- Build testbench infrastructure and verification components
- Create verification item lists, coverage models, and checkers
- Provide clear, metric-driven reports on verification progress
- Break down tasks, develop schedules, and manage deliverables
- Lead and coordinate design review meetings
- Serve as a technical expert and mentor within the team
Key Qualifications:
- Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) with 15+ years of relevant experience
- Extensive hands-on experience creating test environments from functional specifications using UVM/VMM/OVM
- Proven expertise in constraint random verification, coverage closure, and failure analysis
- Proficiency in SystemVerilog, UVM, and object-oriented verification methodologies
- Experience with Verilog/SystemVerilog coding and simulation tools
- Solid understanding of SoC/ASIC design flows and backend processes
- Knowledge of one or more interface protocols: DDR, PCIe, AMBA (AMBA2, AXI, CHI), SD, eMMC, Ethernet, USB, MIPI
- Experience working in Unix environments
- Strong English communication skills, both written and verbal
- Ability to work independently, drive innovation, and solve complex problems
- Strong team player with excellent interpersonal skills
Preferred Qualifications:
- Experience with formal verification techniques
- Knowledge of C/C++, Perl, Python, and TCL scripting
- Understanding of firmware or embedded software development
- Experience with functional safety standards (ISO26262, FMEDA)
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Frequently asked questions
What skills are required for Principal ASIC Design Verification Engineer at Synopsys?
The required skills for Principal ASIC Design Verification Engineer at Synopsys include: SystemVerilog, Verilog, PCIe, Ethernet, Unix, C++, Perl, Python.
What is the seniority level for Principal ASIC Design Verification Engineer at Synopsys?
Principal ASIC Design Verification Engineer at Synopsys is a Principal level position.
How do I apply for Principal ASIC Design Verification Engineer at Synopsys?
You can view the full description and apply for Principal ASIC Design Verification Engineer at Synopsys on EchoJobs: https://echojobs.io/job/synopsys-asic-design-verification-engineer-principal-0ajjq.