Product Engineer for SLM

Interfaces with top-level customer engineers and managers to develop or enhance complex computer-aided engineering design or manufacturing processes for a customer. Uses complex design and tooling tasks involving multiple design environments. Cogently communicates software problems to product development. Assists other engineers in the design, development, and implementation of large scale, complex graphical application programs on multiple software products and hardware platforms. Provides business and technical feedback to software and hardware vendors. Uses advanced data exchange methodologies to facilitate effective data sharing between dissimilar systems or applications that span across engineering disciplines. Responsible for in-depth technical papers and presentations to customer management. Technical Lead in guiding junior engineers. Works without supervision on highly complex projects with latitude for independent judgment and discretion. Extensive knowledge of the field.

Tasks

• Execute proof of concept experiments with monitor/instrument partners (Movellus, AnalogBits, MonIC, proteanTecs, etc.), database/analytics partners (Altair, Plotly (used by d-Matrix for fleet analytics), Siemens ScLM, SLM, customer-developed (e.g. Meta) etc.), and/or early adopter customers (E.g. Intel, Microsoft, Nvidia) 
  • Insertion/integration (IJTAG, EA infrastructure, SSN), instrument wrapping, data capture, logging, file formats, analytics
  • FPGA, ATE, bench, SLT, in-system, in-field
  • Requirement and spec development: From sensor location, insertion, pattern creation, data formatting, data capture methodology, to analytics
  • Example: flow for inserting  & executing pT sensors for Ericsson (lead to production-ready ATPG patterns) - Currently done bye Srujitha

• Development and deployment of diagnostics software for end systems 
• Deployment of applications on cloud (AWS, Azure, Google cloud, etc.)
• Help ensure and verify Tessent SLM flows and capabilities adhere to customer security requirements
  • Insertion security mechanisms
  • Deployment of security solutions and compatibility of end-point
  • Secure access and transmission of data for in-field applications
• Data analytics dashboard creation for internal experimentation and customer applications
  • Based on data from NPI, production test, and-or in-field (timestamped, time series database, etc)
  • Machine Learning / AI approaches

Qualifications

• Needed skills:

  • Bachelor’s or Master’s degree in Electrical or Computer engineering

  • Minimum 8 year experience in the field of Design for Test 

  • Must have industry experience with DFT tools, preferably Tessent tool suite such as TestKompress, SSN, IJTAG, In-system Test

  • Industry experience of or exposure to sensors/monitors for IC designs that provide process monitoring, voltage monitoring, temperature monitoring, etc. 

  • Industry experience with FPGA design development and prototyping

  • Knowledge of databases, visualization tools and packages for semiconductor analytics
  • Experience with semiconductor industry security protocols and standards. 
  • Experience with microservice development for diagnostics
  • Familiarity with deployment of applications on cloud (AWS, Azure, Google cloud, etc.)
  • Proficient in scripting languages such as Python, TCL, etc.

  • The candidate should be high energy, curious individual, self-motivated to learn new test and silicon lifecycle management (SLM) methodologies and technologies, able to work as individual contributor and lead technical activities of junior engineers.

  • Good reasoning and deduction skills and the ability to analyze and debug failing simulations to a successful solution.

  • Able to collaborate and share information across team boundaries in written forum

  • Able to present technical information in a meaningful way to other technical and non-technical audiences

• Nice to have skills:

  • Knowledge of HSIO functional interfaces such as PCIe or USB and their usage for Design for Test

  • Industry experience with processor level debug (Arm, x86, and/or RISC-V platforms)
  • Industry experience with the application of patterns in a tester environment (Automatic Test Equipment (ATE) or System Level Test (SLT)).
  • Industry experience of functional verification techniques using UVM tasks, PSS, emulators and VIP.

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