Sr. Staff Physical Design PPA Engineer

Location: 3900 N Capital of Texas Hwy, Austin, TX, USA

Remote Type: On-site

Time Type: Full time

Job Description

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

As a Sr Staff Physical Design PPA Engineer. you will be responsible for developing and innovating design recipes aimed at improving Power/Performance/Area used for Physical Design execution on SARC/ACL premium IPs.  The role requires a contributor with strong problem-solving skills, high proficiency in all areas of Physical Design Implementation, and a comprehensive approach to delivering solutions.

Key responsibilities include:

• You will lead PPA initiatives by identifying opportunities, tracking progress, and executing towards delivering solutions that meet project requirements.

• You will drive flows and methodologies improvements for the purpose of automating Physical Design Implementation, leveraging your strong problem-solving skills and high proficiency in all areas of Physical Design. You will collaborate with stakeholders to ensure that your solutions meet their needs and expectations.

• You will have hands-on responsibility from synthesis to place and route of an IP block through signoff flows, including timing and physical verification. You will work on synthesis, floor planning, place & route in chip-level and hierarchical physical implementation environments, ensuring that your designs meet PPA targets and signoff requirements.

• You will interact with RTL counterparts and SOC teams to resolve design issues pertaining to block closure, providing feedback and working together to optimize the design flow. You will utilize your comprehensive approach to delivering solutions, ensuring that y

  your work is of the highest quality and meets or exceeds expectations for frequency, power, and area requirements.

Skills and Qualifications

• 10+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master’s degree, or 6+ years of experience with a PhD

• Solid understanding of the SOC/ASIC design flow with particular experience in taping out designs

• Experience with synthesis, block, and full chip implementation utilizing the latest industry P&R/STA flows and tools

• Experience in block level floor-planning, implementing power grid and area/congestion optimization

• Proficient scripting/programming skills in TCL, Perl, Shell, and/or Python

• Knowledge of Electrical Engineering fundamentals, analytical aptitude and excellent attention to detail

• Strong communication skills, team player working in collaborative work environment, discipline and planning; ability to execute with high quality deliverables is a must

Preferred candidate will possess the following:

• Experience with 7nm Finfet or smaller process nodes

• Hands-on experience with clock tree synthesis (CTS)

• Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure

Our Team

We’re strengthening our team of talented individuals with diverse skill sets to build a technology roadmap and deliver market-leading GPU. Our Xclipse GPU is the first mobile GPU with ray tracing technology that enables console-level graphic for Samsung Galaxy smartphones. With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Our Physical Design group is part of the larger Design Implementation team at SARC/ACL. The fast-paced environment here provides us opportunities to learn different areas of design implementation and diversifying our technical expertise. We take pride in our highly collaborative team culture and feel supported by our leadership to explore new ideas and bring them to reality every day. We believe in connecting your area of expertise with the right level and functional discipline that can empower you to grow.

Total Rewards

At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $180,200 and $270,400. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location.

Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.

Additionally, this role might be eligible to participate in long term incentive plan and relocation.

This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions.  Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Trade Secrets

By submitting an application, you [applicant] agree[s] not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity.

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