Design Verification Engineer ( pipeline experience)
Location: Bengaluru, KA, in
Company Description
This job is located in Gachibowli, Hyderabad, India 500032
The VISC™ architecture offers 2-3 times instructions per cycle (IPC) speedup, with up to 4 times performance per watt over today's leading-edge CPUs. The VISC architecture is based on virtual cores that permit one processor thread to operate concurrently on multiple processor cores, overcoming many single-core frequency and power-scaling issues, and multicore programming challenges. VISC also includes a virtual software layer that makes it portable to all CPU ISAs and ecosystems.
"Delivering the first VISC processor and SoCs is a major achievement for our pioneering microprocessor architecture," stated Soft Machines Co-founder, Vice Chairman and CEO Mahesh Lingareddy. "We have received several proposals and are working with customers to define Shasta VISC designs for multiple ISAs, virtual core configurations and SoC features to be delivered in 2016."
"The Shasta VISC processor is designed to deliver server-class performance within mobile power envelopes," said Soft Machines Co-founder, President and CTO Mohammad Abdallah. "Shasta can be configured for dual or quad 64-bit virtual cores, providing a step-function in performance per watt on platforms ranging from smartphones and tablets to laptops and servers."
Job Description
This job is located in Gachibowli, Hyderabad, India 500032
Responsible for pre-silicon RTL verification of a complex low power, high performance design that includes digital and analog cores. Some of the responsibilities include but not limited to testbench/testplans development, block level verification, full-chip verification, coverage driven verification, system & architectural compatibility verification and assertions driven verification. You will also be responsible for mentoring and training junior Engineers.
Qualifications
* 1+ year of industrial experience in pre-silicon verification
* Hands on experience with System Verilog, NTB/VERA, SPECMAN, C/C++ and Perl
* Core CPU Design Verification experience ( AMD ARM APPLE INTEL NVIDIA ORACLE Qualcomm)
* Assembly language test writing/debug is a plus, as is familiarity with UVM/OVM
Additional Information
Soft Machines – India
SMSilicon India Private Limited
Kapil Towers, Financial District,
Gachibowli, Hyderabad, India 500032
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