Yield Diagnostics Engineer, up to staff

Location: Hsinchu City, Taiwan

Department: ASICS Engineering

Work Location: onsite

Company:

Qualcomm Semiconductor Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

We are seeking a highly driven engineer to lead yield analysis & diagnostics across digital and high-voltage product lines. This role emphasizes data-driven yield improvement, scalable diagnostics, and automation, enabling faster root cause resolution and robust high-volume manufacturing. The ideal candidate will bring strong technical depth, agility, and a mindset focused on building repeatable, efficient yield engineering solutions. You will work cross-functionally with foundry, test, product, and quality teams to systematically identify yield limiters and drive sustainable improvement across the product lifecycle.

Key Responsibilities:

• Drive end-to-end yield analysis across wafer sort, final test, and system-level screening
• Identify yield detractors through statistical data mining, failure signature analysis, and silicon correlation
• Lead cross-functional root cause analysis (RCA) and corrective actions with foundry, test, and process integration teams
• Develop and scale yield monitoring frameworks, KPIs, and automated dashboards
• Drive automation and methodology improvements to increase engineering efficiency and scalability

Qualifications:

• M.S. or Ph.D. in Electrical Engineering or a related field, with 5+ years of relevant industry experience.
• Strong experience in yield analytics, diagnostics, and semiconductor data analysis.
• Proven track record of driving yield improvement in high-volume manufacturing environments.
• Solid understanding of Digital design architecture, DFT methodologies (scan, ATPG, etc.), and Test flows including ATE and SLT

Preferred Qualifications:

• Strong knowledge of high-voltage devices (e.g., LDMOS) and ability to interpret device characteristics
• Experience with semiconductor process integration and hands-on experience supporting yield ramp in high-volume manufacturing
• Deep expertise in scan diagnosis techniques and tools for volume yield analysis
• Hands-on experience applying ML/AI techniques in yield analytics and diagnostics

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

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