Video Codec Digital Circuit Design Engineer

Location: Taipei, Taipei City, Taiwan

Department: ASICS Engineering

Work Location: onsite

Company:

Qualcomm Semiconductor Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

• Job Description:
  
  • Architect, design, and optimize hardware blocks for video encoding and decoding, including motion estimation, motion compensation, transform/quantization, entropy coding, in loop filters, and rate control related datapaths.
  
  • Translate video standard requirements (H.264/AVC, H.265/HEVC, AV1, VVC, etc.) into efficient micro architectures and hardware algorithms, ensuring scalability, configurability, and compliance.
  
  • Build C/C++/SystemC models for performance, accuracy, and power estimation; perform algorithm to hardware decomposition to guide RTL implementation. (Consistent with modeling and algorithm decomposition responsibilities in internal files.) [Video HWSYS Engineer | Word]
  
  • Partner with the systems and architecture teams to evaluate codec performance and analyze key KPIs such as throughput, latency, memory bandwidth, and quality metrics.
  
  • Collaborate with verification teams to define test plans, functional coverage, and debug infrastructure for robust pre silicon validation.
  
  • Drive integration of codec IP into SoC subsystems, ensuring seamless interaction with memory subsystems, firmware interfaces, and NoC/fabric components.
  
  • Work with physical design teams to meet PPA targets through timing aware micro architecture, pipeline optimization, and clock/power domain planning.
  
  • Support post silicon bring up and validation, analyze real chip performance, and propose architectural or firmware updates when needed. 
   
• Video Codec Digital Circuit Design Engineer
• Job Location: Taipei

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field.

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