Standard Cell Layout Design Engineer

Location: Tijuana, Baja California, Mexico

Department: ASICS Engineering

Work Location: onsite

Company:

Job Area:

General Summary:

Job Summary:

• As a member of the Qualcomm Standard Cell Design team, the candidate will be responsible for contributing to the development of high-quality intellectual property (IP) for advanced semiconductor technology nodes. This role involves applying strong technical expertise and creativity to deliver efficient and scalable physical layout designs within Qualcomm’s structured and methodical design framework. The position offers significant opportunities for professional and engineering growth through exposure to industry-leading design practices and cutting-edge technologies

Job description:

• Design and develop physical layouts for logic standard cells using industry-standard computer-aided design (CAD) tools, such as Cadence Virtuoso. This role involves leveraging scripting and algorithmic programming languages, including SKILL and Python, to support layout automation, optimization, and design efficiency.
• Perform comprehensive layout verification, including Design Rule Checks (DRC), Layout Versus Schematic (LVS), and Electrical Rule Checks (ERC).
• Collaborate closely with circuit designers to ensure layouts meet quality, performance, and reliability requirements.
• Maintain and manage layout databases using designated Design Management software.
• Engage with the engineering design team to understand design concepts, constraints, and project milestones; accurately and concisely communicate design status and track schedules.
• Proactively and independently identify and resolve design- and PDK-related issues; clearly document and communicate solutions to layout and engineering stakeholders.
• Work closely with Circuit Designers and Mask Layout Designers across global development sites, including the United States, Taiwan, and India.
• Demonstrate strong communication skills and effective teamwork while contributing efficiently within a globally distributed engineering team.

Minimum Qualifications:

• Associate’s degree or technical certificate in Computer Science, Mathematics, Electrical Engineering, or a related discipline.
• Foundational understanding of CMOS technology and integrated circuit (IC) design principles.
• Strong attention to detail with the ability to work effectively in a collaborative team environment.

Preferred Qualifications:

• Bachelor’s degree in Computer Science, Engineering, or a related field.
• Knowledge of parasitic effects and reliability considerations in advanced IC designs.
• Familiarity with scripting and automation languages, such as SKILL and Python, for layout development and optimization.
• Exposure to advanced semiconductor process technologies, including FinFET and Gate-All-Around (GAA) nodes, is a plus.

Minimum Qualifications:

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