This individual independently plans, performs the package designs related to substrate technology and package substrate manufacturing. This involves optimizing system co-design of IC-PKG-PCB die, keeping in mind package footprint/height constraints, IC floor-planning, PCB, high-speed signal integrity, power distribution network, material selection and high volume manufacturing processes. System level co-design methodology of IC, Package and PCB/Board. Know-how and experience in assembly processes, best known materials and method selection. Concept analysis for new product package selection based on requirements for mechanical, thermal and electrical performance with the goal to achieve lowest system level cost. Package design flow methodology implementing high speed interface SI constraints for jitter, IR drop, cross-talk, and SSN specs. Package design flow methodology implementing power distribution network (PDN) constraints for high speed processor cores (1GHz+) including design optimization techniques at the die/pkg/PCB levels. Responsible for setting technology roadmap for substrate technology development as well as driving technology development through new product introduction and sustaining quality in high volume manufacturing. Work with Substrate vendors to develop substrate manufacturing processes and process input and output parameters to enable Qualcomm s next generation premium tier and lower tier chipsets. Acts as a strong contributor at design reviews and project meetings.

Will accept a Master's Degree (or foreign academic equivalent) in Electrical Engineering or related degree field and three (3) years of experience in a related occupation. Will also accept a Bachelor's Degree (or foreign academic equivalent) in Electrical Engineering or related degree field and seven (7) years of progressive experience in a related occupation. Employer will accept any suitable combination of education, training or experience.