SoC Infrastructure IP System HW Architect - RAS

GENERAL SUMMARY

The infrastructure IP Team consists of a multi-disciplinary group involved in the definition and design of Platform infrastructure HW components such as Interconnect (NOC), System Cache, Memory controllers and System MMU that are implemented in all Qualcomm SoCs. This position primarily involves defining HW architecture for the next generation of SOC Infra HW IPs with ARM Architecture enabled and beyond. The ideal candidate should demonstrate the ability to define HW architectures based on Product Requirements and HW-SW interfaces that are SW developer friendly. It requires deep understanding of HW architecture, HW-&-SW feature trade-off, and the complete silicon HW end-2-end design flow. This is a challenging position, defining and driving our most innovative technologies.

Skills/Experience

• Strong knowledge in HW RAS (Reliability, Accessibility, Serviceability) architecture
• Hands-on Experience to define HW RAS architecture and methods to detect-recovery-minimize faults deployed in IO Devices, D2D/C2C and High RAS requirement markets
• Good Knowledge of Software Flow to support HW RAS features
• Good Knowledge of Silicon Failure Analysis to detect and localize failure in the field
• Strong knowledge in SOC and Infrastructure IP (NOC, SMMU, Caches) HW architecture
• Strong knowledge in Quality of Service, Clocks, Power management, Security and Debug architectures and their respective software interfaces
• Good knowledge in industry standard Interconnect Protocol and IO Devices Protocol
• Good knowledge in HW-SW interfaces and firmware
• Experience / knowledge with split multi-die / chiplet architectures
• Experience with Performance modeling and validation
• Experience with RTL design and complete design flow
• Ability to quickly react and adapt to changes.
• Excellent communication skills.

Preferred Qualifications

• Strong knowledge in HW RAS (Reliability, Accessibility, Serviceability) architecture
• Experience in HW RAS architecture definition or Hands-on RAS design/verification is a plus
• Strong knowledge in SOC infrastructure IP (NOC, Caches, SMMU, Memory Controller, Interrupt Handler)
• Strong knowledge in Platform System Architecture (example : ARM or X86 or RISC-V )
• Strong knowledge in ARM Advanced Technology in the area of Security, RAS,  MPAM, Memory Tagging, ….
• Strong knowledge in HW-SW interfaces, APIs & firmware
• Experience with industry standards (PCIe, USB, UFS, MIPI, UCIe,…)
• Experience in Data Science, Machine Learning is a plus
• Experience in Functional Safety is a plus