This individual leads the team to improve engineering efficiency, product quality and responsibility of understanding design specifications and define the verification scope. Develop detailed test plans and verification infrastructure. Implement and execute verification test cases and debug complex issues. Implement and analyze System Verilog assertions and coverage (code, toggle, functional). Work closely with architects, designers, and pre and post-silicon verification teams to accomplish tasks. Develop innovative solutions to verification challenges with minimal guidance. Ramp-up on new verification tools and methodologies. Explore innovative DV methodologies to continuously push the quality and efficiency of test benches. Maintain quality standards and best practices in test and verification processes. Collaborate with design, verification, silicon, and architecture teams to achieve all project goals. Lead the development of verification stimulus models using the industry standard Portable Test and Stimulus Standard (PSS). Design and implement new verification methodologies for complex, scenario based test generation, and provide technical guidance and mentorship to team members in adopting these approaches. Drive the implementation of innovative stimulus modeling techniques to enhance functional coverage, scalability, and reuse across verification environments. Continuously improve design verification quality by standardizing best practices, identifying gaps in existing methodologies, and enabling more robust and comprehensive validation of system level behaviors. Act as a strong contributor at design reviews and project meetings and communicates and implements a development plan.