Security IP DV Sr Lead Engineer

Minimum Exp Level should be 6+ years in IP level verification Good in system Verilog and UVM Concept. Should have good understanding and in hand experience in developing testbench from scratch and aware of all TB environment concept. Should be good in Debugging design by using VCS tool. Good understanding of digital and Verilog concept. Preferrable to have experience in Security related IP like cryptography and prng and RSA algorithms. Preferrable to have understanding in SiFive RISC processor. Good understanding in basic bus protocol like AHB/AXI/APB. Good understanding in Functional/Code coverage. Good to have Formal tool knowledge either VCF or Jasper gold.