We are seeking a seasoned ISP / Video DRAM Access & Arbitration Design Engineer to join our SoC design team. In this role, you will architect and develop end to end DRAM access pipelines, arbitration mechanisms, bandwidth governance strategies, and QoS frameworks that enable high performance image and video processing in advanced semiconductor products. You will help define micro architecture, traffic models, simulation methodology, and performance KPIs that ensure predictable latency, robust throughput, and efficient DRAM utilization under complex multi stream workloads.
You will collaborate closely with ISP/Video architects, NoC/interconnect teams, memory controller designers, performance modeling engineers, firmware developers, and verification teams to deliver highly scalable DRAM access solutions supporting camera pipelines, multi frame HDR, noise reduction, rotation, video encode/decode, and concurrent multimedia workloads.
This position requires strong technical depth in multimedia traffic behavior and memory system architecture, coupled with hands on design expertise to translate diverse performance and QoS requirements into efficient, production ready hardware and policies.

Responsibilities:

1.    Architect DRAM access pipelines for ISP and Video workloads, including read/write scheduling, burst shaping, buffering, and scalable support for high resolution and multi stream scenarios.
2.    Design and optimize arbitration and QoS mechanisms—such as priority based, aging, credit/token based, fairness, and deadline/urgency policies—to ensure deterministic latency for real time imaging and video paths.
3.    Develop performance and traffic models (C/C++/SystemC/Python) to analyze DRAM bandwidth, latency, utilization, and to evaluate arbitration and QoS strategies across representative workloads.
4.    Collaborate cross functionally with ISP/Video architecture, NoC/interconnect, and memory controller teams to align system level dataflows, bandwidth budgets, and runtime QoS requirements.
5.    Support verification and post silicon validation, including DRAM trace analysis, bandwidth/latency profiling, QoS tuning, issue debug, and preparation of architecture/performance documentation.

Minimum Qualifications:

•     Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
•    Strong understanding of DRAM systems (LPDDR4/5), memory controller scheduling, row/bank/refresh behavior, and SoC memory hierarchy.
•    Solid knowledge of ISP and Video dataflow patterns, including RAW/YUV access, multi frame fusion, motion/ME pipelines, and video reference frame behavior.
•    Proficiency in RTL micro architecture, performance analysis, and modeling using SystemVerilog, SystemC, C++, and/or Python.
•    Experience analyzing bandwidth, latency, utilization, and backpressure effects in complex SoC environments.
•    Demonstrated ability to drive designs from concept through modeling, implementation, and silicon validation.

Preferred Qualifications:

•    Experience with DRAM access design for ISP or video pipelines such as HDR, noise reduction, rotation/warp, or video encoder/decoder flows.
•    Background in NoC/MC arbitration, QoS tuning, bandwidth shaping, and pre silicon performance modeling.
•    Familiarity with multi subsystem concurrency across camera, video, display, CPU/GPU/AI pipelines and system level bandwidth planning.
•    Experience with post silicon performance profiling, QoS analysis, and DRAM trace based debugging.
•    Strong cross team communication skills and the ability to work across ISP/Video/Display/ML architecture groups.